Abstract: A dual packet configuration for wireless communications including a first portion that is modulated according to a serial modulation and a second portion that is modulated according to a parallel modulation. The serial modulation may be DSSS whereas the parallel modulation may be OFDM. The first portion may include a header, which may further include an OFDM mode bit and a length field indicating the duration the second portion. The first portion may be in accordance with 802.11b to enable dual mode devices to coexist and communicate in the same area as standard 802.11b devices. The dual mode devices can communicate at different or higher data rates without interruption from the 802.11b devices. The packet configuration may include an OFDM signal symbol which further includes a data rate section and a data count section. In this manner, data rates the same as or similar to the 802.11a data rates may be specified between dual mode devices.

Abstract: Disclosed herein are various embodiments of methods, systems, and apparatuses for sending and receiving signals in a digital communication system. In one embodiment performs steps of transmitting a signal from a device with a first antenna array and calibrating the signal with a phase shift of the signal. In one exemplary method embodiment, a signal is transmitted from a beam-forming transmitter to an assisting receiver in an IEEE 802.11 wireless transmission. A return calibration signal from the assisting receiver with information regarding the phase error of signal is received by the beam-forming transceiver. The beam-forming transmitter introduces a calibration phase error to cancel the phase error as reported by the assisting receiver.

Abstract: A 10 MHz channelized orthogonal frequency division multiplexing (OFDM) transmitter is provided that communicates using a modified OFDM packet structure with a half-rate oscillator having standard accuracy. The transmitter has an inverse fast fourier transform (IFFT) data processor that appends an outer pair of data subcarriers on either end of an OFDM subcarrier profile. An IFFT long sync processor appends an outer pair of binary phase shift key (BPSK) subcarriers on either end of an OFDM long sync subcarrier profile. By copying or appending the information of the data subcarriers closest to zero Hz. to more robust locations, 10 MHz channelized OFDM can be achieved with half-rate clocks and 20 PPM oscillators.

Abstract: A power-based hardware antenna diversity method for a wireless transceiver with multiple antennas is disclosed. The method is characterized in the steps of setting the transceiver gain at a maximum level to establish a first story of dynamic power range above a noise floor level, using a high-resolution ADC at a large back-off level relative to the noise floor to detect weak signals within the first story of the dynamic power range, switching antennas and measuring power level for each antenna during signal onset, and selecting an antenna having a largest power level.

Abstract: An adaptive frequency equalization system providing an equalizer that has programmable taps that adjusts magnitude and phase of symbol information of a received signal and that provides equalized symbol information. The system includes a hard decision circuit that selects ideal symbol values using the equalized symbol information. A frequency response circuit determines frequency response update values using the ideal symbol values and the received signal. An adjust circuit updates stored frequency response information using the frequency response update values, and also updates the programmable taps of the equalizer using the stored frequency response information.