Patents by Inventor Steven Harshfield

Steven Harshfield has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080017953
    Abstract: Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching.
    Type: Application
    Filed: December 31, 2002
    Publication date: January 24, 2008
    Inventor: Steven Harshfield
  • Publication number: 20080012000
    Abstract: A method and an apparatus for manufacturing a memory cell having a non-volatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A recessed plug of a conductive material is then formed within a lower portion of the opening and a dielectric spacer is formed along the sidewalls of an upper portion of the opening. The spacer is cylindrical and has a central hole. A contact plug is subsequently formed within the central hole, the contact plug electrically coupled to the recessed plug. The contact plug can include a memory element or an additional memory element can be applied over the contact plug.
    Type: Application
    Filed: September 18, 2007
    Publication date: January 17, 2008
    Inventor: Steven Harshfield
  • Publication number: 20070235712
    Abstract: An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material is disposed over the plated electrode and subjected to a conversion process so that ions from the plated material diffuse into the chalcogenide material.
    Type: Application
    Filed: May 22, 2007
    Publication date: October 11, 2007
    Inventors: Steven Harshfield, David Wright
  • Publication number: 20070012987
    Abstract: Methods are provided for selective formation of oxidation-resistant caps for conductive plugs in semiconductor device fabrication. One embodiment of the present invention forms a sacrificial layer over a recessed polysilicon plug. The sacrificial layer is readily planarized using chemical mechanical planarization to isolate the cap within a recessed via. Then, an immersion plating process is used to replace the atoms of the sacrificial layer with atoms of a desired metal, such as platinum, thereby creating a metal cap isolated within the via. The advantages of planarization to isolate material within recessed via are thus obtained without having to planarize or otherwise etch the desired metal. The cap layer can be further reacted to form a barrier compound prior to forming a capacitor over the plug. Advantageously, the plug structure resists oxidation during fabrication of overlying capacitors that incorporate high dielectric constant materials.
    Type: Application
    Filed: July 18, 2006
    Publication date: January 18, 2007
    Inventors: Allen McTeer, Steven Harshfield
  • Publication number: 20060099822
    Abstract: An inverted PCRAM cell is formed by plating the bottom electrode, made of copper for example, with a conductive material, such as silver. Chalcogenide material is disposed over the plated electrode and subjected to a conversion process so that ions from the plated material diffuse into the chalcogenide material.
    Type: Application
    Filed: December 14, 2005
    Publication date: May 11, 2006
    Inventors: Steven Harshfield, David Wright
  • Publication number: 20050029587
    Abstract: A method and an apparatus for manufacturing a memory cell having a non-volatile resistive memory element with a limited size active area. The method comprises a first step of providing a dielectric volume and forming a plug opening within the dielectric volume. A recessed plug of a conductive material is then formed within a lower portion of the opening and a dielectric spacer is formed along the sidewalls of an upper portion of the opening. The spacer is cylindrical and has a central hole. A contact plug is subsequently formed within the central hole, the contact plug electrically coupled to the recessed plug. The contact plug can include a memory element or an additional memory element can be applied over the contact plug.
    Type: Application
    Filed: August 31, 2004
    Publication date: February 10, 2005
    Inventor: Steven Harshfield