Abstract: A shielded cable interface module having cable receiving grooves extending laterally to an edge of the board, each including a center conductor groove, an insulator groove, and a shield groove. A center conductor via and a shield via extend through the board. A conductor plane on the cable termination side surrounds the cable receiving grooves. The conductor plane includes a non-conductor region within the conductor plane adjacent to each of the conductor center conductor grooves. Ground vias associated with the cable receiving grooves are spaced apart from and partially surround the center conductor via outside and adjacent to the non-conductor region, the ground vias extend through the printed circuit board from the cable termination side to the system interface side.

Abstract: A shielded cable interface module having cable receiving grooves extending laterally to an edge of the board, each including a center conductor groove, an insulator groove, and a shield groove. A center conductor via and a shield via extend through the board. A conductor plane on the cable termination side surrounds the cable receiving grooves. The conductor plane includes a non-conductor region within the conductor plane adjacent to each of the conductor center conductor grooves. Ground vias associated with the cable receiving grooves are spaced apart from and partially surround the center conductor via outside and adjacent to the non-conductor region, the ground vias extend through the printed circuit board from the cable termination side to the system interface side.

Abstract: A printed circuit board assembly adapted for immersion cooling is disclosed. The assembly includes a first circuit board having a first device side with a first portion configured to mount a first plurality of semiconductor devices. A second circuit board having a second device side with a second portion configured to mount a second plurality of semiconductor devices is disposed in confronting parallel relationship to the first circuit board. The assembly further includes a border element interposed between the first and second boards and disposed around the respective first and second portions. The border element cooperates with the first and second boards to form a liquid-tight container. An inlet formed in the border receives an electrically nonconducting liquid that is subsequently discharged through an outlet.

Abstract: A printed circuit board assembly adapted for immersion cooling is disclosed. The assembly includes a first circuit board having a first device side with a first portion configured to mount a first plurality of semiconductor devices. A second circuit board having a second device side with a second portion configured to mount a second plurality of semiconductor devices is disposed in confronting parallel relationship to the first circuit board. The assembly further includes a border element interposed between the first and second boards and disposed around the respective first and second portions. The border element cooperates with the first and second boards to form a liquid-tight container. An inlet formed in the border receives an electrically nonconducting liquid that is subsequently discharged through an outlet.

Abstract: In at least one embodiment, a circuit for a multi-channel tester having a central resource, a plurality of outputs, and a switching matrix coupling the central resource to the plurality of outputs via a plurality of selectable channels. Each of the selectable channels having PIN diodes coupled in a half-bridge configuration. A first, a second, and a third biasing source for forward biasing the PIN diodes. The first and second biasing sources are coupled to a central resource coupled end and an output coupled end of the half-bridge, respectively. The third biasing source is coupled to a common node. The first and second biasing sources are constructed to provide substantially balanced outputs and such that the sum of the outputs of the first and second biasing sources are substantially balanced with respect to the output of the third bias source. In some embodiments, a the plurality of selectable channels comprises the same first biasing source.

Abstract: In at least one embodiment, a circuit for a multi-channel tester having a central resource, a plurality of outputs, and a switching matrix coupling the central resource to the plurality of outputs via a plurality of selectable channels. Each of the selectable channels having PIN diodes coupled in a half-bridge configuration. A first, a second, and a third biasing source for forward biasing the PIN diodes. The first and second biasing sources are coupled to a central resource coupled end and an output coupled end of the half-bridge, respectively. The third biasing source is coupled to a common node. The first and second biasing sources are constructed to provide substantially balanced outputs and such that the sum of the outputs of the first and second biasing sources are substantially balanced with respect to the output of the third bias source. In some embodiments, a the plurality of selectable channels comprises the same first biasing source.

Abstract: An apparatus for testing and calibration in automated test equipment includes a time varying signal channel having a series-connected solid state switch interposed between a time varying signal circuit end and a device under test end of the time varying signal channel. A DC test channel is connected to the time varying signal channel between the series-connected solid state switch and the device under test end, and has at least one solid state switch interposed along the DC test channel to provide switchable coupling between a DC parametrics circuit side of the DC test channel and the time varying signal channel.