Patents by Inventor Steven Hiloong WELCH

Steven Hiloong WELCH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11880137
    Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.
    Type: Grant
    Filed: March 23, 2023
    Date of Patent: January 23, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Huixiong Dai, Mangesh Ashok Bangar, Srinivas D. Nemani, Ellie Y. Yieh, Steven Hiloong Welch, Christopher S. Ngai
  • Patent number: 11798606
    Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: October 24, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: John O. Dukovic, Srinivas D. Nemani, Ellie Y. Yieh, Praburam Gopalraja, Steven Hiloong Welch, Bhargav S. Citla
  • Publication number: 20230229089
    Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.
    Type: Application
    Filed: March 23, 2023
    Publication date: July 20, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Huixiong DAI, Mangesh Ashok BANGAR, Srinivas D. NEMANI, Ellie Y. YIEH, Steven Hiloong WELCH, Christopher S. NGAI
  • Patent number: 11650506
    Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: May 16, 2023
    Assignee: Applied Materials Inc.
    Inventors: Huixiong Dai, Mangesh Bangar, Christopher S. Ngai, Srinivas D. Nemani, Ellie Y. Yieh, Steven Hiloong Welch
  • Publication number: 20220390847
    Abstract: A method for processing a substrate is described. The method includes forming a metal containing resist layer onto a substrate, patterning the metal containing resist layer, and performing a post exposure bake on the metal containing resist layer. The post exposure bake on the metal containing resist layer is a field guided post exposure bake operation and includes the use of an electric field to guide the ions or charged species within the metal containing resist layer. The field guided post exposure bake operation may be paired with a post development field guided bake operation.
    Type: Application
    Filed: June 8, 2021
    Publication date: December 8, 2022
    Inventors: Huixiong DAI, Mangesh Ashok BANGAR, Srinivas D. NEMANI, Steven Hiloong WELCH, Ellie Y. YIEH, Dmitry LUBOMIRSKY
  • Publication number: 20210305501
    Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 30, 2021
    Inventors: John O. DUKOVIC, Srinivas D. NEMANI, Ellie Y. YIEH, Praburam GOPALRAJA, Steven Hiloong WELCH, Bhargav S. CITLA
  • Publication number: 20210294215
    Abstract: A method for enhancing a photoresist profile control includes applying a photoresist layer comprising a photoacid generator on an underlayer disposed on a material layer, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and drifting photoacid from the photoresist layer to a predetermined portion of the underlayer under the first portion of the photoresist layer.
    Type: Application
    Filed: March 20, 2020
    Publication date: September 23, 2021
    Inventors: Huixiong DAI, Srinivas D. NEMANI, Steven Hiloong WELCH, Mangesh Ashok BANGAR, Ellie Y. YIEH
  • Patent number: 11049537
    Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: John O. Dukovic, Srinivas D. Nemani, Ellie Y. Yieh, Praburam Gopalraja, Steven Hiloong Welch, Bhargav S. Citla
  • Publication number: 20210088896
    Abstract: Embodiments of the disclosure relate to lithography simulation and optical proximity correction. Field-guided post exposure bake processes have enabled improved lithography performance and various parameters of such processes are included in the optical proximity correction models generated in accordance with the embodiments described herein. An optical proximity correction model includes one or more parameters of anisotropic acid etching characteristics, ion generation and/or movement, electron movement, hole movement, and chemical reaction characteristics.
    Type: Application
    Filed: August 3, 2020
    Publication date: March 25, 2021
    Inventors: Huixiong DAI, Mangesh Ashok BANGAR, Pinkesh Rohit SHAH, Srinivas D. NEMANI, Steven Hiloong WELCH, Christopher Siu Wing NGAI, Ellie Y. YIEH
  • Publication number: 20210035619
    Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.
    Type: Application
    Filed: July 29, 2019
    Publication date: February 4, 2021
    Inventors: John O. DUKOVIC, Srinivas D. NEMANI, Ellie Y. YIEH, Praburam GOPALRAJA, Steven Hiloong WELCH, Bhargav S. CITLA
  • Publication number: 20200233307
    Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.
    Type: Application
    Filed: October 11, 2019
    Publication date: July 23, 2020
    Inventors: Huixiong DAI, Mangesh BANGAR, Christopher S. NGAI, Srinivas D. NEMANI, Ellie Y. YIEH, Steven Hiloong WELCH