Patents by Inventor Steven Hiloong WELCH
Steven Hiloong WELCH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11880137Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.Type: GrantFiled: March 23, 2023Date of Patent: January 23, 2024Assignee: Applied Materials, Inc.Inventors: Huixiong Dai, Mangesh Ashok Bangar, Srinivas D. Nemani, Ellie Y. Yieh, Steven Hiloong Welch, Christopher S. Ngai
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Patent number: 11798606Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.Type: GrantFiled: May 24, 2021Date of Patent: October 24, 2023Assignee: APPLIED MATERIALS, INC.Inventors: John O. Dukovic, Srinivas D. Nemani, Ellie Y. Yieh, Praburam Gopalraja, Steven Hiloong Welch, Bhargav S. Citla
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Publication number: 20230229089Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.Type: ApplicationFiled: March 23, 2023Publication date: July 20, 2023Applicant: Applied Materials, Inc.Inventors: Huixiong DAI, Mangesh Ashok BANGAR, Srinivas D. NEMANI, Ellie Y. YIEH, Steven Hiloong WELCH, Christopher S. NGAI
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Patent number: 11650506Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.Type: GrantFiled: October 11, 2019Date of Patent: May 16, 2023Assignee: Applied Materials Inc.Inventors: Huixiong Dai, Mangesh Bangar, Christopher S. Ngai, Srinivas D. Nemani, Ellie Y. Yieh, Steven Hiloong Welch
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Publication number: 20220390847Abstract: A method for processing a substrate is described. The method includes forming a metal containing resist layer onto a substrate, patterning the metal containing resist layer, and performing a post exposure bake on the metal containing resist layer. The post exposure bake on the metal containing resist layer is a field guided post exposure bake operation and includes the use of an electric field to guide the ions or charged species within the metal containing resist layer. The field guided post exposure bake operation may be paired with a post development field guided bake operation.Type: ApplicationFiled: June 8, 2021Publication date: December 8, 2022Inventors: Huixiong DAI, Mangesh Ashok BANGAR, Srinivas D. NEMANI, Steven Hiloong WELCH, Ellie Y. YIEH, Dmitry LUBOMIRSKY
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Publication number: 20210305501Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.Type: ApplicationFiled: May 24, 2021Publication date: September 30, 2021Inventors: John O. DUKOVIC, Srinivas D. NEMANI, Ellie Y. YIEH, Praburam GOPALRAJA, Steven Hiloong WELCH, Bhargav S. CITLA
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Publication number: 20210294215Abstract: A method for enhancing a photoresist profile control includes applying a photoresist layer comprising a photoacid generator on an underlayer disposed on a material layer, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and drifting photoacid from the photoresist layer to a predetermined portion of the underlayer under the first portion of the photoresist layer.Type: ApplicationFiled: March 20, 2020Publication date: September 23, 2021Inventors: Huixiong DAI, Srinivas D. NEMANI, Steven Hiloong WELCH, Mangesh Ashok BANGAR, Ellie Y. YIEH
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Patent number: 11049537Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.Type: GrantFiled: July 29, 2019Date of Patent: June 29, 2021Assignee: Applied Materials, Inc.Inventors: John O. Dukovic, Srinivas D. Nemani, Ellie Y. Yieh, Praburam Gopalraja, Steven Hiloong Welch, Bhargav S. Citla
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Publication number: 20210088896Abstract: Embodiments of the disclosure relate to lithography simulation and optical proximity correction. Field-guided post exposure bake processes have enabled improved lithography performance and various parameters of such processes are included in the optical proximity correction models generated in accordance with the embodiments described herein. An optical proximity correction model includes one or more parameters of anisotropic acid etching characteristics, ion generation and/or movement, electron movement, hole movement, and chemical reaction characteristics.Type: ApplicationFiled: August 3, 2020Publication date: March 25, 2021Inventors: Huixiong DAI, Mangesh Ashok BANGAR, Pinkesh Rohit SHAH, Srinivas D. NEMANI, Steven Hiloong WELCH, Christopher Siu Wing NGAI, Ellie Y. YIEH
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Publication number: 20210035619Abstract: One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.Type: ApplicationFiled: July 29, 2019Publication date: February 4, 2021Inventors: John O. DUKOVIC, Srinivas D. NEMANI, Ellie Y. YIEH, Praburam GOPALRAJA, Steven Hiloong WELCH, Bhargav S. CITLA
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Publication number: 20200233307Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate includes applying a photoresist layer comprising a photoacid generator to on a multi-layer disposed on a substrate, wherein the multi-layer comprises an underlayer formed from an organic material, inorganic material, or a mixture of organic and inorganic materials, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.Type: ApplicationFiled: October 11, 2019Publication date: July 23, 2020Inventors: Huixiong DAI, Mangesh BANGAR, Christopher S. NGAI, Srinivas D. NEMANI, Ellie Y. YIEH, Steven Hiloong WELCH