Abstract: The use of Black Solider Fly Larvae as Palatant/Palatability Enhancer for use in edible pet products This invention disclosed a palatability enhancer for edible pet products using black solider fly (Hermetia illucens) larvae, wherein the black solider fly larvae are collected following the commercial farming, the greater part of the materials being processed for safety and size reduced as necessary, at 10.0%-80.0%. The palatability enhancer may also include at least one of the following: Cysteine, Arginine, Alanine, Glutamine, Aspartic acid, Glycine, Phenylalanine, Isoleucine, Histidine, Vitamin B1, and a reducing sugar, at 0.1%-10.0% by weight.

Abstract: A palatability enhancer composition for edible pet products comprises Cysteine and Arginine, at 0.1%-10.0% by weight; and Lysine at 0.1%-10.0% by weight. The palatability enhancer may also include at least one of the following: Alanine, Glutamine, Aspartic acid, Glycine, Phenylalanine, Isoleucine, Histidine, Vitamin B1, and a reducing sugar, at 0.1%-10.0% by weight.

Abstract: A method of low-latency and encrypted hardware layer communication includes calculating, by an encryption circuit of a communication bridge controller, a pre-calculated encryption keys corresponding to a block encryptor of the encryption circuit, each block encryptor configured to use a corresponding pre-calculated encryption key to encrypt a corresponding unencrypted data block of a data transmission having one or more unencrypted data blocks, storing the one or more pre-calculated encryption keys in an encryption key memory associated with the communication bridge, for each unecrypted data block, encrypting the unencrypted data block using the corresponding pre-calculated encryption key to generate an encrypted data block and an authentication code block for the unencrypted data block, aggregating one or more encrypted data blocks into an encrypted data transmission, and generating an authenticated code corresponding to the encrypted data transmission based upon each of the authentication code blocks of eac

Abstract: A separating system for separating or separating items formed in a cavity of an injection molding system to separate them from material in the mold's runner, has a clamp plate for anchoring the separator system. The clamp plate secures a separating plate that supports a first separating pin, either directly or via an actuator. The first separating pin includes a base, a body having a cross-sectional portion, a neck having a cross-sectional portion, and a wedge-shaped tip. The system includes a support plate that supports a cavity plate, where the cavity plate has a first cavity and a first gate that fluidly couples the first cavity to a first runner channel. The separating first separating pin can be articulated to separate a molded material at a boundary between the first gate and the first cavity.

Abstract: The present invention provides for functional chimeric gene regulatory units capable of driving strong and sustained heterologous gene expression.

Abstract: The present invention provides for functional chimeric gene regulatory units capable of driving strong and sustained heterologous gene expression.

Abstract: This invention relates to nucleic acid molecules comprising at least one nucleic acid sequence encoding for a peptide or protein of interest, at least one nucleic acid sequence encoding for a selectable marker, and at least one IRES sequence, wherein the at least one IRES sequence is located between the at least one nucleic acid sequence encoding for the peptide or protein of interest and the at least one nucleic acid sequence encoding for the selectable marker. Furthermore, this invention relates to host cells comprising such nucleic acid molecule and to methods of recombinant protein expression using such host cells.

Abstract: This invention relates to nucleic acid molecules comprising at least one nucleic acid sequence encoding for a peptide or protein of interest, at least one nucleic acid sequence encoding for a selectable marker, and at least one IRES sequence, wherein the at least one IRES sequence is located between the at least one nucleic acid sequence encoding for the peptide or protein of interest and the at least one nucleic acid sequence encoding for the selectable marker. Furthermore, this invention relates to host cells comprising such nucleic acid molecule and to methods of recombinant protein expression using such host cells.

Abstract: A cochlear implant wherein the return path of the electrode array is located to increase current flow through the modiolus. The return electrode is placed at various locations outside the cochlea, and into the modiolus itself. In addition, the electrode array includes an inflatable membrane that is inflated to anchor the array in position in the cochlea with the electrode contacts pressed into contact with the modiolar wall and allowing the membrane to seal with the surrounding tissue of the cochlea, increasing the longitudinal resistance along the cochlear implant electrode, decreasing shunting of the injected current via scala tympani. In experiments that were conducted the current along the modiolus was determined to be, on average, 2.4 times larger with the return electrode in the modiolus than in an extracochlear location.

Abstract: A system and method avoids passive release of interrupts in a computer system. The computer system includes a plurality of processors, a plurality of input/output (I/O) devices each capable of issuing interrupts, and an I/O bridge interfacing between the I/O devices and the processors. Interrupts, such as level sensitive interrupts (LSIs), asserted by an I/O device coupled to a specific port of the I/O bridge are sent to a processor for servicing by an interrupt controller, which also sets an interrupt pending flag. Upon dispatching the respective interrupt service routine, the processor generates two ordered messages. The first ordered message is sent to the I/O device that triggered the interrupt, informing it that the interrupt has been serviced. The second ordered message directs the interrupt controller to clear the respective interrupt pending flag. Both messages are sent, in order, to the particular I/O bridge port to which the subject I/O device is coupled.

Abstract: A system and method avoids “livelock” and “starvation” among two or more input/output (I/O) devices of a symmetrical multiprocessor (SMP) computer system competing for the same data. The SMP computer system includes a plurality of interconnected processors, one or more memories that are shared by the processors, and a plurality of I/O bridges to which the I/O devices are coupled. A cache coherency protocol is executed the I/O bridges, which requires the I/O bridges to obtain “exclusive” (not shared) ownership of all data stored by the bridges. In response to a request for data currently stored by an I/O bridge, the bridge first copies at least a portion of that data to a non-coherent buffer before invalidating the data. The bridge then takes the largest amount of the data saved in its non-coherent buffer that its knows to be coherent, and releases only that known coherent amount to the I/O device, and then discards all of the saved data.

Abstract: A system and method avoids “livelock” and “starvation” among two or more input/output (I/O) devices of a symmetrical multiprocessor (SMP) computer system competing for the same data. The SMP computer system includes a plurality of interconnected processors, one or more memories that are shared by the processors, and a plurality of I/O bridges to which the I/O devices are coupled. A cache coherency protocol is executed the I/O bridges, which requires the I/O bridges to obtain “exclusive” (not shared) ownership of all data stored by the bridges. In response to a request for data currently stored by an I/O bridge, the bridge first copies at least a portion of that data to a non-coherent buffer before invalidating the data. The bridge then takes the largest amount of the data saved in its non-coherent buffer that its knows to be coherent, and releases only that known coherent amount to the I/O device, and then discards all of the saved data.

Abstract: A method and apparatus for accommodating the speed requirements of a DMA read request from PCI protocol I/O devices attached via a DMA to a multiprocessor system mesh. A bridge between the device controller and the mesh is described which buffers the data from the memory in cache lines from which the data is delivered finally to the I/O device. The system is adaptive in that the number of cache lines required in past reads are remembered and used to determine if the number of cache lines is reduced or increased.

Abstract: A system and method avoids “livelock” and “starvation” among two or more input/output (I/O) devices of a symmetrical multiprocessor (SMP) computer system competing for the same data. The SMP computer system includes a plurality of interconnected processors, one or more memories that are shared by the processors, and a plurality of I/O bridges to which the I/O devices are coupled. A cache coherency protocol is executed the I/O bridges, which requires the I/O bridges to obtain “exclusive” (not shared) ownership of all data stored by the bridges. In response to a request for data currently stored by an I/O bridge, the bridge first copies at least a portion of that data to a non-coherent buffer before invalidating the data. The bridge then takes the largest amount of the data saved in its non-coherent buffer that its knows to be coherent, and releases only that known coherent amount to the I/O device, and then discards all of the saved data.

Abstract: A system and method avoids passive release of interrupts in a computer system. The computer system includes a plurality of processors, a plurality of input/output (I/O) devices each capable of issuing interrupts, and an I/O bridge interfacing between the I/O devices and the processors. Interrupts, such as level sensitive interrupts (LSIs), asserted by an I/O device coupled to a specific port of the I/O bridge are sent to a processor for servicing by an interrupt controller, which also sets an interrupt pending flag. Upon dispatching the respective interrupt service routine, the processor generates two ordered messages. The first ordered message is sent to the I/O device that triggered the interrupt, informing it that the interrupt has been serviced. The second ordered message directs the interrupt controller to clear the respective interrupt pending flag. Both messages are sent, in order, to the particular I/O bridge port to which the subject I/O device is coupled.

Abstract: A technique provides data from an information signal. The technique involves receiving the information signal in the forwarded clock device synchronously with a forwarded clock signal. The technique further involves recovering data contained within the information signal synchronously with a recovery clock signal such that the data is recovered with (i) a particular cycle latency when the recovery clock signal has an optimal rate for the forwarded clock device, and (ii) a different cycle latency when the recovery clock signal has a sub-optimal rate. The particular cycle latency may include more cycles than the different cycle latency. As such, the time latency may be shorter when the recovery clock signal has the sub-optimal rate.

Abstract: A method and system for controlling the operations of a multi-processor system in a programmable fashion that allows tuning of the operational flow including support for hot swapping. A system control register or registers with a plurality of fields are defined to allocate system resources available at I/O ports to anticipated transactions at those ports. The control register(s) fields may include, for each port, the number of direct memory access engines available to support transactions, the number of cache lines available for requested data, the priorities of the anticipated transactions, etc. One field supports hot swapping wherein the registers, memory and cache contents and status are flushed and stored and the system directory is updated. Also, and the status of data with respect to the swapped assembly is updated to inform the system.

Abstract: A method for shimming a magnetic resonance imaging magnet requiring higher magnetic field homogneity on a small imaging volume and by magnetic field measurements on a larger volume providing small measurement error and practical field strength measurements and utilizing the spherical harmonic coefficients of the measurements.