Abstract: Radio Frequency Identification (RFID) tags are provided, along with apparatuses and methods for making. In some embodiments, the RFID tags include an RFID tag chip that is attached to an inlay and/or a strap. The inlay or strap has one or more contact bumps formed thereon. In some of these embodiments, the RFID tag chip includes pads for electrical contacts, but not chip-bumps, thanks to the contact bump.

Abstract: Radio Frequency Identification (RFID) tags are provided, along with apparatuses and methods for making. In some embodiments, the RFID tags include an RFID tag chip that is attached to an inlay and/or a strap. The inlay or strap has one or more contact bumps formed thereon. In some of these embodiments, the RFID tag chip includes pads for electrical contacts, but not chip-bumps, thanks to the contact bump.

Abstract: A non-volatile memory (NVM) circuit is provided, that includes at least a first and second NVM sub-array. The first sub-array is built from first memory cells. The second NVM sub-array is built from second memory cells that are constructed differently from the first memory cells. The NVM sub-arrays share a support circuit. In some embodiments the sub-arrays can be constructed, so that they exhibit different characteristics tailored to their intended use. For example one sub-array might be tailored for data retention, while the next sub-array for programming endurance, still another for write disturb immunity.

Abstract: A non-volatile memory (NVM) circuit is provided, that includes at least a first and second NVM sub-array. The first sub-array is built from first memory cells. The second NVM sub-array is built from second memory cells that are constructed differently from the first memory cells. The NVM sub-arrays share a support circuit. In some embodiments the sub-arrays can be constructed, so that they exhibit different characteristics tailored to their intended use. For example one sub-array might be tailored for data retention, while the next sub-array for programming endurance, still another for write disturb immunity.

Abstract: A non-volatile memory (NVM) circuit is provided, that includes at least a first and second NVM sub-array. The first sub-array is built from first memory cells. The second NVM sub-array is built from second memory cells that are constructed differently from the first memory cells. The NVM sub-arrays share a support circuit. In some embodiments the sub-arrays can be constructed, so that they exhibit different characteristics tailored to their intended use. For example one sub-array might be tailored for data retention, while the next sub-array for programming endurance, still another for write disturb immunity.

Abstract: A test system including a data center, controller, interface, and device under test. The data center generates a test program which is applied to the device under test by the controller via the interface. The device under test includes circuitry structured for testing. The test system identifies the location of faulty elements on the device under test and stores these locations for use in a subsequent repair step.