Patents by Inventor Steven J. Adler
Steven J. Adler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230298946Abstract: An integrated circuit includes a bipolar transistor extending into a [100] surface of a semiconductor substrate having a crystalline lattice. A deep trench surrounds the bipolar transistor and has a path having a plurality of sides. At least one side extends in a direction parallel to a <100> axis of the crystalline lattice.Type: ApplicationFiled: December 30, 2022Publication date: September 21, 2023Inventors: Abbas Ali, Rajni J. Aggarwal, Steven J Adler
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Publication number: 20230060695Abstract: An electronic device comprises a semiconductor substrate including majority carrier dopants of a first conductivity type, a semiconductor surface layer including majority carrier dopants of a second conductivity type, field oxide that extends on the semiconductor surface layer, and an isolation structure. The isolation structure includes a trench that extends through the semiconductor surface layer and into one of the semiconductor substrate and a buried layer of the semiconductor substrate, and polysilicon including majority carrier dopants of the second conductivity type, the polysilicon fills the trench to a side of the semiconductor surface layer.Type: ApplicationFiled: August 31, 2021Publication date: March 2, 2023Applicant: Texas Instruments IncorporatedInventors: Abbas Ali, Rajni J. Aggarwal, Steven J. Adler, Eugene C. Davis
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Patent number: 10741687Abstract: A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.Type: GrantFiled: July 10, 2017Date of Patent: August 11, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yaojian Leng, Richard Foote, Steven J. Adler
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Publication number: 20170309743Abstract: A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.Type: ApplicationFiled: July 10, 2017Publication date: October 26, 2017Inventors: Yaojian Leng, Richard Foote, Steven J. Adler
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Patent number: 9716167Abstract: A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.Type: GrantFiled: February 22, 2011Date of Patent: July 25, 2017Assignee: National Semiconductor CorporationInventors: Yaojian Leng, Richard Wendell Foote, Jr., Steven J. Adler
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Patent number: 8563345Abstract: A method for forming a capacitive micromachined ultrasonic transducer (CMUT) includes forming multiple CMUT elements in a first semiconductor-on-insulator (SOI) structure. Each CMUT element includes multiple CMUT cells. The first SOI structure includes a first handle wafer, a first buried layer, and a first active layer. The method also includes forming a membrane over the CMUT elements and forming electrical contacts through the first handle wafer and the first buried layer. The electrical contacts are in electrical connection with the CMUT elements. The membrane could be formed by bonding a second SOI structure to the first SOI structure, where the second SOI structure includes a second handle wafer, a second buried layer, and a second active layer. The second handle wafer and the second buried layer can be removed, and the membrane includes the second active layer.Type: GrantFiled: March 13, 2012Date of Patent: October 22, 2013Assignee: National Semiconductor CorporatedInventors: Steven J. Adler, Peter Johnson, Gokhan Percin, Shahram Mostafazadeh
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Publication number: 20130001647Abstract: In an embodiment, a bipolar transistor structure is formed on a silicon-on-insulator (SOI) structure that includes a semiconductor substrate, a buried oxide layer formed on the semiconductor substrate and a top silicon layer formed on the buried oxide layer.Type: ApplicationFiled: June 28, 2011Publication date: January 3, 2013Inventor: Steven J. Adler
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Patent number: 8324006Abstract: A method includes forming first isolation trenches in a first side of a first semiconductor-on-insulator (SOI) structure to electrically isolate multiple portions of the first SOI structure from each other. The method also includes bonding a second SOI structure to the first SOI structure to form multiple cavities between the SOI structures. The method further includes forming conductive plugs through a second side of the first SOI structure and forming second isolation trenches in the second side of the first SOI structure around the conductive plugs. In addition, the method includes removing portions of the second SOI structure to leave a membrane bonded to the first SOI structure. The isolated portions of the first SOI structure, the cavities, and the membrane form multiple capacitive micromachined ultrasonic transducer (CMUT) elements. Each CMUT element is formed in one of the isolated portions of the first SOI structure and includes multiple CMUT cells.Type: GrantFiled: October 28, 2009Date of Patent: December 4, 2012Assignee: National Semiconductor CorporationInventors: Steven J. Adler, Peter Johnson, Ira Wygant
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Publication number: 20120211826Abstract: A trench DMOS transistor with a very low on-state drain-to-source resistance and a high gate-to-drain charge includes one or more floating islands that lie between the gate and drain to reduce the charge coupling between the gate and drain, and effectively lower the gate-to-drain capacitance.Type: ApplicationFiled: February 22, 2011Publication date: August 23, 2012Inventors: Yaojian Leng, Richard Wendell Foote, JR., Steven J. Adler
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Publication number: 20120187508Abstract: A method for forming a capacitive micromachined ultrasonic transducer (CMUT) includes forming multiple CMUT elements in a first semiconductor-on-insulator (SOI) structure. Each CMUT element includes multiple CMUT cells. The first SOI structure includes a first handle wafer, a first buried layer, and a first active layer. The method also includes forming a membrane over the CMUT elements and forming electrical contacts through the first handle wafer and the first buried layer. The electrical contacts are in electrical connection with the CMUT elements. The membrane could be formed by bonding a second SOI structure to the first SOI structure, where the second SOI structure includes a second handle wafer, a second buried layer, and a second active layer. The second handle wafer and the second buried layer can be removed, and the membrane includes the second active layer.Type: ApplicationFiled: March 13, 2012Publication date: July 26, 2012Applicant: Texas Instruments IncorporatedInventors: Steven J. Adler, Peter Johnson, Gokhan Percin, Shahram Mostafazadeh
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Patent number: 7927958Abstract: A system and method are disclosed for providing a self aligned bipolar transistor using a silicon nitride ring. An active region of the transistor is formed and a sacrificial emitter is formed above the active region of the transistor. A silicon nitride ring is formed around the sacrificial emitter. The sacrificial emitter and the silicon nitride ring are formed by depositing a layer of silicon nitride material over the active area of the transistor and performing an etch process to simultaneously create both the sacrificial emitter and the silicon nitride ring. The silicon nitride ring provides support for forming a raised external base for the transistor.Type: GrantFiled: May 15, 2007Date of Patent: April 19, 2011Assignee: National Semiconductor CorporationInventors: Mingwei Xu, Steven J. Adler
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Patent number: 7910447Abstract: A system and method are disclosed for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter. An active region of a transistor is formed and a silicon nitride sacrificial emitter is formed above the active region of the transistor. Then a physical vapor deposition oxide layer is deposited over the silicon nitride sacrificial emitter using a physical vapor deposition process. The physical vapor deposition oxide layer is then etched away from the side walls of the sacrificial emitter. The sacrificial emitter is then etched away to form an emitter window. Then a polysilicon emitter structure is formed in the emitter window. The self aligned bipolar transistor architecture of the invention is compatible with BiCMOS technology.Type: GrantFiled: May 15, 2007Date of Patent: March 22, 2011Assignee: National Semiconductor CorporationInventors: Mingwei Xu, Steven J. Adler
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Patent number: 7884023Abstract: An electronic apparatus is disclosed that comprises a silicon nitride material that has an increased silicon content. The silicon nitride material is manufactured by exposing plasma enhanced chemical vapor deposition (PECVD) silicon nitride to an increased flow of silane while the PECVD silicon nitride is being deposited. The material has anti-reflective coating (ARC) properties and can also be used as a hard mask. When the material is covered with cobalt the material forms conductive cobalt silicide when the cobalt is annealed. A method for siliciding the PECVD silicon nitride is also disclosed.Type: GrantFiled: September 12, 2005Date of Patent: February 8, 2011Assignee: National Semiconductor CorporationInventors: Heather E. McCulloh, Patrick McCarthy, Steven J. Adler, Henry G. Prosack, Jr.
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Patent number: 7781295Abstract: A system and method is disclosed for manufacturing a bipolar junction transistor that comprises an emitter/base layer that is formed by a single deposition process. In one advantageous embodiment of the invention the emitter/base layer comprises an emitter layer that comprises an epitaxially grown mono-silicon emitter. The epitaxially grown mono-silicon emitter significantly reduces the electrical resistivity of the emitter. A non-dopant impurity such as germanium is added to the base layer to endpoint a dry plasma etch process that is applied to etch the emitter/base layer.Type: GrantFiled: July 13, 2006Date of Patent: August 24, 2010Assignee: National Semiconductor CorporationInventors: Jamal Ramdani, Craig Printy, Steven J. Adler, Andre P. Labonte
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Patent number: 7678657Abstract: A system and method are disclosed for manufacturing an emitter structure in a complementary bipolar complementary metal oxide semiconductor (CBiCMOS) transistor manufacturing process. A protective layer is formed over an emitter layer in a transistor structure and lateral portions of the protective layer and the emitter layer are etched to form an emitter structure. An oxide layer is then deposited over the transistor structure and an etchback process is performed to remove portions of the oxide layer from the top of the protective layer. A source/drain implant process is then performed to implant an extrinsic base region of the transistor. The protective layer protects the emitter structure from the implant process. Then the protective layer is removed from the emitter structure.Type: GrantFiled: November 2, 2006Date of Patent: March 16, 2010Assignee: National Semiconductor CorporationInventors: Todd Patrick Thibeault, Steven J. Adler, Scott David Ruby
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Patent number: 7642168Abstract: A system and method are disclosed for providing a self aligned bipolar transistor using a sacrificial polysilicon external base. An active region of a transistor is formed and a sacrificial polysilicon external base is formed above the active region of the transistor and covered with a silicon oxide layer. Then an emitter window is etched and filled with silicon nitride. An etch procedure is subsequently performed to remove the sacrificial polysilicon external base. A layer of doped polysilicon material is then deposited to fill a cavity within the transistor formed by the removal of the sacrificial polysilicon external base. A polysilicon emitter structure is subsequently formed in the emitter window. The self aligned bipolar transistor architecture of the invention is compatible with BiCMOS technology.Type: GrantFiled: May 18, 2007Date of Patent: January 5, 2010Assignee: National Semiconductor CorporationInventors: Mingwei Xu, Steven J. Adler
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Patent number: 5556793Abstract: A method for gettering metallic impurities from a semiconductor substrate (25). A gettering structure is fabricated in inactive areas of a semiconductor chip (31). The gettering structure is manufactured by forming an oxide (30) having a bird's head structure contacting a heavily doped region (28). The combination creates precipitation nuclei to which the metallic impurities migrate. The metallic impurities are sequestered by the precipitation nuclei or trap sites and rendered incapable of degrading the electrical characteristics of a semiconductor device.Type: GrantFiled: November 1, 1993Date of Patent: September 17, 1996Assignee: Motorola, Inc.Inventors: Steven J. Adler, George W. Hawkins, Israel A. Lesk, Peter L. Pegler, Hassan Pirastehfar
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Patent number: 5371394Abstract: An NMOS transistor has a source and a drain composed of n+ type of semiconductor material. A substrate region composed of a p type of semiconductor material is disposed between the source and the drain. A gate region is disposed above the substrate region and between the source region and the drain region. A first implant region is disposed adjacent to the source region and the gate region. The first implant region is composed of p type of semiconductor material with a first doping concentration. A second implant region is disposed between the first implant region and the substrate. The second implant region is composed of p type of semiconductor material with a second doping concentration. The channel doping profile first and second implant regions is tailored to obtain the optimum internal electric field to maximize device transconductance, while simultaneously controlling the device threshold voltage and punch through characteristics.Type: GrantFiled: November 15, 1993Date of Patent: December 6, 1994Assignee: Motorola, Inc.Inventors: Gordon C. Ma, Hassan Pirastehfar, Steven J. Adler
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Patent number: 5252848Abstract: A performance enhancing conductor (27) is employed to reduce a transistor's (10) on resistance and to also reduce the transistor's (10) parasitic gate to drain capacitance (32). The performance enhancing conductor (27) covers the transistor's (10) gate (22) and a portion of the drain region (18, 19) that is adjacent the transistor's channel (20). The performance enhancing conductor (27) is isolated from the gate (22) by an insulator (24, 26).Type: GrantFiled: February 3, 1992Date of Patent: October 12, 1993Assignee: Motorola, Inc.Inventors: Steven J. Adler, Robert B. Davies, Stephen J. Nugent, Hassan Pirastehfar