Patents by Inventor STEVEN J. BATTLE
STEVEN J. BATTLE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200341767Abstract: An aspect includes receiving a flush request at a processing unit that is in a current state defined by contents of registers in a register file. The processing unit includes a plurality of slices and the flush request includes an identifier of a previously issued instruction. The processing unit is restored to a previous state defined by contents of the registers in the register file prior to the previously issued instruction being issued. The restoring includes searching previous state buffers in at least two of the plurality of slices to locate data describing the contents of the registers in the register file prior to the previously issued instruction being issued. The restoring also includes combining the located data to generate results of the searching and updating the contents of the registers in the register file using a single port based at least in part on the results.Type: ApplicationFiled: April 24, 2019Publication date: October 29, 2020Inventors: Steven J. Battle, Brandon Goddard, Dung Q. Nguyen, Joshua W. Bowman, Brian D. Barrick, Susan Eisen, Salma Ayub, Christopher M. Mueller
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Publication number: 20200326978Abstract: A non-limiting example of a computer-implemented method for file register writes using pointers includes, responsive to a dispatch instruction, storing, at a location in a history buffer, an instruction tag and first data associated with the instruction tag. The method further includes storing a pointer in an issue queue. The pointer points to the location in the history buffer. The method further includes performing a write back of second data using the pointer stored in the issue queue. The write back writes the second data into the location of the history buffer associated with the pointer.Type: ApplicationFiled: April 15, 2019Publication date: October 15, 2020Inventors: Brian D. Barrick, Steven J. Battle, Joshua W. Bowman, Cliff Kucharski, Hung Q. Le, Dung Q. Nguyen, David R. Terry
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Publication number: 20200301758Abstract: A processor configured to manage a transaction memory (TM) state. The processor is configured to receive a first instruction indicating a start of a speculative transaction and update a register file with a speculative transaction memory (TM) state corresponding to the speculative transaction. The processor is further configured to determine whether or not the register file is able to store the entirety of speculative TM state. If the register file is unable to store the entirety of the speculative TM state, the processor is configured to copy a previous TM (pre-TM) state from the register file to a memory which is external to the processor. Further, the processor may be configured to complete updating the register file with the speculative TM state after the pre-TM state has been copied from the register file to the memory.Type: ApplicationFiled: March 21, 2019Publication date: September 24, 2020Inventors: Steven J. BATTLE, Dung Q. NGUYEN, Hung Q. LE, James W. BISHOP, Brian W. THOMPTO, Susan E. EISEN
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Patent number: 10740140Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor for processing instructions, the processor having a history buffer having a plurality of entries for storing information associated with a processor instruction evicted from a logical register, the history buffer having at least one recovery port; a logical register mapper for recovering information from the history buffer, the mapper having restore ports to recover information from the history buffer; and a restore multiplexor configured to receive as inputs information from one or more of the history buffer recovery ports, and configured to output information to one or more of the logical register mapper restore ports. The processor, system and/or method configured to improve flush recovery bandwidth.Type: GrantFiled: November 16, 2018Date of Patent: August 11, 2020Assignee: International Business Machines CorporationInventors: Steven J. Battle, Khandker Nabil Adeeb, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Jamory Hawkins, Dung Q. Nguyen
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Publication number: 20200241931Abstract: Recovering microprocessor logical register values by: partitioning a register mapper by logical register type; providing a plurality of recovery ports; assigning a logical register type to a recovery port; receiving a restore required instruction; and mapping SRB (save and restore buffer) values to the register mapper by logical register type.Type: ApplicationFiled: January 25, 2019Publication date: July 30, 2020Inventors: Steven J. Battle, Brandon R. Goddard, Dung Q. Nguyen, Joshua W. Bowman, Brian D. Barrick, Susan E. Eisen, David S. Walder, Cliff Kucharski
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Publication number: 20200201639Abstract: A computer system includes a dispatch routing network to dispatch a plurality of instructions, and a processor in signal communication with the dispatch routing network. The processor determines a move instruction from the plurality of instructions to move data produced by an older second instruction, and copies a splice target file (STF) tag from a source register of the move instruction to a destination register of the move instruction without physically copying data in a slice target register and without assigning a new STF tag destination to the move instruction.Type: ApplicationFiled: December 20, 2018Publication date: June 25, 2020Inventors: Joshua Bowman, Dung Q. Nguyen, Hung Le, Brian Thompto, Maureen A. Delaney, Cliff Kucharski, Steven J Battle
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Publication number: 20200183700Abstract: A computer system, processor, and method for processing information is disclosed that includes partitioning a logical register in the processor into a plurality of ranges of logical register entries based upon the logical register entry, assigning at least one recovery port of a history buffer to each range of logical register entries, initiating a flush recovery process for the processor, and directing history buffer entries to the assigned recovery port based upon the logical register entry associated with the history buffer entry.Type: ApplicationFiled: December 5, 2018Publication date: June 11, 2020Inventors: Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Christopher M. Mueller, Dung Q. Nguyen
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Publication number: 20200183701Abstract: A computer system, processor, and method for processing information is disclosed that includes reading out a plurality of entries in a history buffer prior to initiating a flush recovery process; initiating the flush recovery process; determining which of the history buffer entries read out of the history buffer should be recovered; and sending information associated with the history buffer entries to be recovered to one or more history buffer recovery ports. In one or more embodiments, the history buffer entries are continually read out in response to a processor and history buffer entries read out from the history buffer are directed to a specific history buffer recovery port associated with a mapper of a specific logical register.Type: ApplicationFiled: December 5, 2018Publication date: June 11, 2020Inventors: Steven J. Battle, Khandker Nabil Adeeb, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Jamory Hawkins, Dung Q. Nguyen
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Publication number: 20200159564Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor for processing instructions, the processor having a history buffer having a plurality of entries for storing information associated with a processor instruction evicted from a logical register, the history buffer having a at least one recovery port; a logical register mapper for recovering information from the history buffer, the mapper having restore ports to recover information from the history buffer; and a restore multiplexor configured to receive as inputs information from one or more of the history buffer recovery ports, and configured to output information to one or more of the logical register mapper restore ports. The processor, system and/or method configured to improve flush recovery bandwidth.Type: ApplicationFiled: November 16, 2018Publication date: May 21, 2020Inventors: Steven J. Battle, Khandker Nabil Adeeb, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Jamory Hawkins, Dung Q. Nguyen
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Publication number: 20200081713Abstract: An approach is provided in which a system writes a set of data into a register file entry that includes a first memory array and a second memory array. The register file entry also includes a set of first write ports corresponding to the first memory array and a set of second write ports corresponding to the second memory array. The system configures a selection bit based on determining that a selected one of the set of first write ports is utilized to store the set of data in the first memory array. In turn, the system reads the set of data out of the first memory array based on the configured selection bit.Type: ApplicationFiled: September 6, 2018Publication date: March 12, 2020Inventors: Saiful Islam, Sam G. Chu, Dung Q. Nguyen, Binglong Zhang, Howard Levy, David R. Terry, Steven J. Battle
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Patent number: 10564691Abstract: Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.Type: GrantFiled: November 3, 2017Date of Patent: February 18, 2020Assignee: International Business Machines CorporationInventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino
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Patent number: 10545765Abstract: Embodiments include systems, methods, and computer program products for using a multi-level history buffer (HB) for a speculative transaction. One method includes after dispatching a first instruction indicating start of the speculative transaction, marking one or more register file (RF) entries as pre-transaction memory (PTM), and after dispatching a second instruction targeting one of the marked RF entries, moving data from the marked RF entry to a first level HB entry and marking the first level HB entry as PTM. The method also includes upon detecting a write back to the first level HB entry, moving data from the first level HB entry to a second level HB entry and marking the second level HB entry as PTM. The method further includes upon determining that the second level HB entry has been completed, moving data from the second level HB entry to a third level HB entry.Type: GrantFiled: May 17, 2017Date of Patent: January 28, 2020Assignee: International Business Machines CorporationInventors: Brian D. Barrick, Steven J. Battle, Joshua W. Bowman, Hung Q. Le, Dung Q. Nguyen, David R. Terry, Albert J. Van Norstrand, Jr.
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Publication number: 20200019405Abstract: A split level history buffer in a central processing unit is provided. The history buffer includes first, second, and third levels, each having different characteristics. Operational instructions are provided to support the split history buffer. A first instruction is fetched, tagged, and stored in an entry of a register file. As a second instruction is fetched and tagged, the first instruction is evicted from the register file and stored in the first level of the history buffer. Similarly, as a result for the first instruction is generated, the first instruction and the generated result are stored in the second level of the history buffer. In response to instruction completion, instead of remaining in the second level, the first instruction, which contains pre-transactional memory checkpoint data, is moved from the second level to the third level of the history buffer, together with pre-transactional memory data, and the first instruction entry in the second level is invalidated.Type: ApplicationFiled: July 15, 2018Publication date: January 16, 2020Applicant: International Business Machines CorporationInventors: Steven J. Battle, Joshua W. Bowman, Dung Q. Nguyen, Albert J. Van Norstrand, JR., Cliff Kucharski, Hung Q. Le, Brian D. Barrick
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Publication number: 20190361698Abstract: A computer system, processor, and method for processing information is disclosed that includes at least one computer processor, a register file associated with the at least one processor, preferably a condition register that stores status information, the register file having multiple locations for storing data, multiple ports to write data to and read data from the register file. The system or processor includes an execution area, and the processor is configured to read from all the read ports in a first cycle, and to read from all the read ports in a second cycle. In an embodiment, the execution area includes a staging latch to store data from a first cycle read operation, and in an aspect the computer system is configured to combine the data stored in the staging latch during a first read cycle with the data read from the second cycle.Type: ApplicationFiled: May 23, 2018Publication date: November 28, 2019Inventors: Steven J. Battle, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Cliff Kucharski, Dung Q. Nguyen, David S. Walder
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Patent number: 10489253Abstract: Embodiments include systems, methods, and computer program products for on-demand error detection and correction of registers in a processor. One method includes detecting, before a first instruction is dispatched to an issue queue in the processor, an error in data, associated with the first instruction, stored in an entry of a register file in the processor. The method also includes, after detecting the error, halting the dispatch of the first instruction to the issue queue, and determining whether the entry of the register file has completed. The method further includes determining whether to perform error correction on the register file based on the determination of whether the entry of the register file has completed.Type: GrantFiled: May 16, 2017Date of Patent: November 26, 2019Assignee: International Business Machines CorporationInventors: Steven J. Battle, Joshua W. Bowman, Sundeep Chadha, Dhivya Jeganathan, Cliff Kucharski, Dung Q. Nguyen, Tu-An T. Nguyen, David R. Terry
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Patent number: 10379867Abstract: Techniques are disclosed for performing a flush and restore of a history buffer (HB) in a processing unit. One technique includes identifying one or more entries of the HB to restore to a register file in the processing unit. For each of the one or more HB entries, a determination is made whether to send the HB entry to the register file via a first restore bus or via a second restore bus, different from the first restore bus, based on contents of the HB entry. Each of the one or more HB entries is then sent to the register file via one of the first restore bus or the second restore bus, based on the determination.Type: GrantFiled: December 18, 2017Date of Patent: August 13, 2019Assignee: International Business Machines CorporationInventors: David R. Terry, Dung Q. Nguyen, Brian W. Thompto, Joshua W. Bowman, Steven J. Battle, Brian D. Barrick, Sundeep Chadha, Albert J. Van Norstrand, Jr.
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Publication number: 20190188133Abstract: Techniques are disclosed for performing issue queue snooping for an asynchronous flush and restore of a history buffer (HB) in a processing unit. One technique includes identifying an entry of the HB to restore to a register file in the processing unit. A restore ITAG of the HB entry is sent to the register file via a first restore bus, and restore data of the HB entry and the restore ITAG is sent to the register file via a second restore bus. After the restore ITAG and restore data are sent, an instruction is dispatched before the register file obtains the restore data. After it is determined that the restore data is still available via the second restore bus, a snooping operation is performed to obtain the restore data from the second restore bus for the dispatched instruction.Type: ApplicationFiled: December 18, 2017Publication date: June 20, 2019Inventors: David R. TERRY, Dung Q. NGUYEN, Brian W. THOMPTO, Joshua W. BOWMAN, Steven J. BATTLE, Sundeep CHADHA, Brian D. BARRICK, Albert J. VAN NORSTRAND, JR.
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Publication number: 20190187995Abstract: Techniques are disclosed for performing a flush and restore of a history buffer (HB) in a processing unit. One technique inludes identifying one or more entries of the HB to restore to a register file in the processing unit. For each of the one or more HB entries, a determination is made whether to send the HB entry to the register file via a first restore bus or via a second restore bus, different from the first restore bus, based on contents of the HB entry. Each of the one or more HB entries is then sent to the register file via one of the first restore bus or the second restore bus, based on the determination.Type: ApplicationFiled: December 18, 2017Publication date: June 20, 2019Inventors: David R. TERRY, Dung Q. NGUYEN, Brian W. THOMPTO, Joshua W. BOWMAN, Steven J. BATTLE, Brian D. BARRICK, Sundeep CHADHA, Albert J. VAN NORSTRAND, JR.
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Publication number: 20190171569Abstract: Embodiments include systems, methods, and computer program products for using a multi-tier hang buster for detecting and breaking out of hang conditions in a processor. One method includes determining a plurality of actions available at each of a plurality of tiers used for breaking out of the hang condition in the processor. The method also includes, after detecting the hang condition on a first thread of the processor, performing one or more actions available at a first tier of the plurality of tiers to break out of the hang condition. The method further includes, after performing the one or more actions at the first tier and determining that the hang condition is still present, performing one or more actions available at one or more second tiers of the plurality of tiers to break out of the hang condition.Type: ApplicationFiled: December 5, 2017Publication date: June 6, 2019Inventors: Steven J. BATTLE, Dung Q. Nguyen, Susan E. Eisen, Kenneth L. Ward, Eula Faye Abalos Tolentino, Cliff Kucharski, Glenn O. Kincaid, David S. Walder
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Patent number: 10296337Abstract: Methods and apparatus for preventing premature reads from a general purpose register (GPR) including receiving an instruction comprising a source operand identifying a source GPR entry; setting a read-enabled flag based on a value in a particular entry of a source ready vector; if the read-enabled flag indicates data in the source GPR entry is ready for reading, dispatching the received instruction, including performing a read operation of the data in the source GPR entry; and if the read-enabled flag indicates data in the source GPR entry is not ready for reading, dispatching the received instruction without performing a read operation of the data in the source GPR entry.Type: GrantFiled: March 21, 2016Date of Patent: May 21, 2019Assignee: International Business Machines CorporationInventors: Steven J. Battle, Owen Chiang, Sam G. Chu, Saiful Islam, Dung Q. Nguyen, David R. Terry, Eula A. Tolentino