Abstract: An alignment circuit for use in a synchronous data transfer system for logically comparing the phase of a returned clock signal having an unknown phase relative to a local clock such that the local clock or its inverse can be used to retime returned remote data without the possibility of generating errors due to the lack of set-up time and hold time requirements for actuating a D flip-flop gate at its clock input with respect to the data arriving a the D input of the D flip-flop. The phase of the local clock relative to the return clock is detected and compared with a threshold phase shift value. If the phase shift is negligible, the remote data is clocked by the inverted local clock. If the phase shift exceeds the threshold value, the remote data is clocked by the local clock.

Abstract: A time division multiplex ring comprising a plurality of nodes connected together by interchanged trunks (main and standby paths) in a ring type or closed loop configuration. Each node in the system includes transmitters and receivers on the main and standby paths along with bridging and switching circuits connected to data failure and other failure detection circuits for operating same arranged such that data and alarm signals are transmitted in the first direction on the main path around the closed loop and in an opposite direction on the standby path. The system is arranged such that if a failure occurs only on the main path and the standby path is unaffected, all communications are switched to the standby path.

Abstract: A simplified digital NRZ data phase detector is provided with a minimum number of components and with an expanded measuring interval to enable the use of slower speed components. In a phase locked loop application, a first input gate, such as a flip-flop, responds to NRZ data, and a second input gate responds to clock pulses and the output of the first gate. Variable and fixed width correction signals are derived directly from the outputs of the first and second gates, respectively, within a measuring interval initiated by a data transition and terminated by a clock transition. The difference in duration between the directly derived variable and fixed pulses provides phase indication.

Abstract: A flip-flop receives clock pulses of frequency F and is alternately set and reset on alternate inverted third clock pulse edges by logic responsive to the clock pulses and to the output of the flip-flop. The logic includes a second flip-flop and a pair of gates which maintain the set and reset states of the first flip-flop for two consecutive clock pulse edges between set and reset transitions to provide symmetrical output pulses from the first flip-flop of frequency 1/3F with a substantially 50% duty cycle.

Abstract: A digital circuit receives symmetrical clock pulses of frequency F and outputs symmetrical pulses of frequency 1/3 F. A divide by one and one-half circuit clocks a divide by two flip-flop resulting in a symmetrical divide by three output. The divide by one and one-half circuit includes a pair of JK flip-flops and logic gates which receive clock pulses of frequency F and generate a plurality of staggered signal streams with nonsymmetrical pulses of frequency 1/3 F and a duty cycle of substantially 33%. The input clock pulses are gated against two of these streams to provide an output pulse during the first half of the duty portion of a cycle of one of the streams, and another output pulse during the second half of the duty portion of a cycle of the other stream, to provide an output frequency of 2/3 F which then clocks the divide by two flip-flop.