Abstract: Test and measurement instrumentation collects time information independently in each clock domain using a device that monotonically changes state with the passage of time according to a local clock domain. The device under test therefore has a unique state for each synchronous time period. The instrumentation periodically samples the devices under test, collects the state of each device, and records the state of the devices in conjunction with any data collected in clock domains that are synchronous with the devices. The periodic samples are transformed into numeric values using an isomorphic or linear model. These values are then fitted to an assumed frequency model that relates the state of devices in otherwise unrelated clock domains.

Abstract: In one general aspect, a data collection system for a circuit under test implemented as an integrated circuit or using a programmable logic device is disclosed. It comprises a configurable selection network connected to debug nodes of the circuit. The selection network can be reconfigured after implementation of the circuit to route data from selectable debug nodes in the circuit under test to a controller to allow analysis of the circuit. The data collection system can further comprise a configurable data packer. A method of use of the system associates data from the debug nodes with individual debug nodes of the circuit based on a configuration of the configurable selection network or that of the configurable data packer or both. The method and system of the invention allows for efficient data collection from different sets of debug nodes without having to re-implement the circuit.

Abstract: Test and measurement instrumentation collects time information independently in each clock domain using a device that monotonically changes state with the passage of time according to a local clock domain. The device under test therefore has a unique state for each synchronous time period. The instrumentation periodically samples the devices under test, collects the state of each device, and records the state of the devices in conjunction with any data collected in clock domains that are synchronous with the devices. The periodic samples are transformed into numeric values using an isomorphic or linear model. These values are then fitted to an assumed frequency model that relates the state of devices in otherwise unrelated clock domains.

Abstract: In one general aspect, a data collection system for a circuit under test implemented as an integrated circuit or using a programmable logic device is disclosed. It comprises a configurable selection network connected to debug nodes of the circuit. The selection network can be reconfigured after implementation of the circuit to route data from selectable debug nodes in the circuit under test to a controller to allow analysis of the circuit. The data collection system can further comprise a configurable data packer. A method of use of the system associates data from the debug nodes with individual debug nodes of the circuit based on a configuration of the configurable selection network or that of the configurable data packer or both. The method and system of the invention allows for efficient data collection from different sets of debug nodes without having to re-implement the circuit.

Abstract: Integrated circuit devices having fixed and programmable logic portions are made by combining a hardware description language representation of the fixed logic and a hardware description language representation of the programmable logic to create a single hardware description language representation of a device. This allows multiple portions of programmable logic, distributed where needed in whatever size needed, to be interspersed among the fixed logic. Because the behavior of the programmable logic, rather than of the user programming, is being represented, a programmable logic architecture is provided that lacks behaviors, such as combinational loops, that would cause compilation of the hardware description language to generate errors.

Abstract: Integrated circuit devices having fixed and programmable logic portions are made by combining a hardware description language representation of the fixed logic and a hardware description language representation of the programmable logic to create a single hardware description language representation of a device. This allows multiple portions of programmable logic, distributed where needed in whatever size needed, to be interspersed among the fixed logic. Because the behavior of the programmable logic, rather than of the user programming, is being represented, a programmable logic architecture is provided that lacks behaviors, such as combinational loops, that would cause compilation of the hardware description language to generate errors.

Abstract: An apparatus comprising one or more configurable interface tiles. The configurable interface tiles may be configured to communicate one or more signals between one or more programmable logic cores and one or more fixed function cores. The one or more configurable interface tiles, the one or more programmable logic cores and the one or more fixed function cores may be integrated on a single chip.

Abstract: A configurable crossbar switching circuit within a programmable logic device capable of efficient, large scale switching and for cascading for implementing much larger switching functions. In one embodiment of the invention, the crossbar switch is integral to a programmable logic device. In one embodiment, the crossbar switching circuit is bus based, switching all of the conductors constituting a data bus substantially simultaneously and in their entirety as a bus unit. In one embodiment, the crossbar switching circuit performs switching operations unidirectionally. For the implementation of larger scale switching functions, one embodiment of the present invention exploits the cascadable character of the crossbar switching circuit. Cascading crossbar switches enables switching between differing numbers of inputs and outputs, even exceeding capacities of individual crossbars.

Abstract: A method and architecture for providing signal paths between a programmable logic core and a fixed function core comprising the steps of (a) coupling one or more first signals between the fixed function core and an interface block configured to couple the fixed function core and the programmable logic core and (b) coupling one or more second signals between the interface block and the programmable logic core.

Abstract: An apparatus comprising one or more memory blocks in a programmable logic device. The memory blocks may be configured as content-addressable memory having arbitrarily adjustable tag and data widths.

Abstract: A configurable crossbar switching circuit within a programmable logic device capable of efficient, large scale switching and for cascading for implementing much larger switching functions. In one embodiment of the invention, the crossbar switch is integral to a programmable logic device. In one embodiment, the crossbar switching circuit is bus based, switching all of the conductors constituting a data bus substantially simultaneously and in their entirety as a bus unit. In one embodiment, the crossbar switching circuit performs switching operations unidirectionally. For the implementation of larger scale switching functions, one embodiment of the present invention exploits the cascadable character of the crossbar switching circuit. Cascading crossbar switches enables switching between differing numbers of inputs and outputs, even exceeding capacities of individual crossbars.