Abstract: An interleaver that implements the LCS turbo interleaver algorithm utilized by the CDMA2000 standard is described. The interleaver includes a first computation unit for receiving an input address and computing a first sequential interleaved address during a first clock cycle in response thereto. A second computation unit is included for receiving an input address and computing a second sequential interleaved address during the first clock cycle in response thereto. The interleaver further includes a comparator for determining whether the first or the second sequential interleaved address is invalid and generating a signal in response thereto. The output of the comparator provides a control signal to a switch which selects the first or the second sequential interleaved address as an output interleaved address for the first clock cycle. The interleaver is further designed to move in a forward direction or a reverse direction.

Abstract: Techniques for polling fingers on a channel (which are fingers for which symbols are to be combined) to determine the last finger on the channel. As each finger is polled, the polled finger compares its state information with the state information for the channel to determine whether or not it is the last finger on the channel. The polled finger may be deemed as the last finger if (1) the polled finger is the current last finger, (2) the polled finger is later than the current last finger, or (3) all fingers on the channel have been polled and none of the fingers indicated that it is the last finger. If the polled finger is deemed as the last finger then, (1) the channel state information is updated with the polled finger state information, and (2) the symbols provided by the polled finger may be marked as being ready for subsequent processing.

Abstract: An interleaver that implements the LCS turbo interleaver algorithm utilized by the CDMA2000 standard is described. The interleaver includes a first computation unit for receiving an input address and computing a first sequential interleaved address during a first clock cycle in response thereto. A second computation unit is included for receiving an input address and computing a second sequential interleaved address during the first clock cycle in response thereto. The interleaver further includes a comparator for determining whether the first or the second sequential interleaved address is invalid and generating a signal in response thereto. The output of the comparator provides a control signal to a switch which selects the first or the second sequential interleaved address as an output interleaved address for the first clock cycle. The interleaver is further designed to move in a forward direction or a reverse direction.

Abstract: An interleaver that implements the LCS turbo interleaver algorithm utilized by the CDMA2000 standard is described. The interleaver includes a first computation unit for receiving an input address and computing a first sequential interleaved address during a first clock cycle in response thereto. A second computation unit is included for receiving an input address and computing a second sequential interleaved address during the first clock cycle in response thereto. The interleaver further includes a comparator for determining whether the first or the second sequential interleaved address is invalid and generating a signal in response thereto. The output of the comparator provides a control signal to a switch which selects the first or the second sequential interleaved address as an output interleaved address for the first clock cycle. The interleaver is further designed to move in a forward direction or a reverse direction.

Abstract: An interleaver that implements the LCS turbo interleaver algorithm utilized by the CDMA2000 standard is described. The interleaver includes a first computation unit for receiving an input address and computing a first sequential interleaved address during a first clock cycle in response thereto. A second computation unit is included for receiving an input address and computing a second sequential interleaved address during the first clock cycle in response thereto. The interleaver further includes a comparator for determining whether the first or the second sequential interleaved address is invalid and generating a signal in response thereto. The output of the comparator provides a control signal to a switch which selects the first or the second sequential interleaved address as an output interleaved address for the first clock cycle. The interleaver is further designed to move in a forward direction or a reverse direction.

Abstract: Techniques for polling fingers on a channel (which are fingers for which symbols are to be combined) to determine the last finger on the channel. As each finger is polled, the polled finger compares its state information with the state information for the channel to determine whether or not it is the last finger on the channel. The polled finger may be deemed as the last finger if (1) the polled finger is the current last finger, (2) the polled finger is later than the current last finger, or (3) all fingers on the channel have been polled and none of the fingers indicated that it is the last finger. If the polled finger is deemed as the last finger then, (1) the channel state information is updated with the polled finger state information, and (2) the symbols provided by the polled finger may be marked as being ready for subsequent processing.

Abstract: The present invention is a novel and improved technique for performing coding with particular application to turbo, or iterative, coding techniques. In accordance with one embodiment of the invention, interleaving is performed by generating the address of a memory using a PN state generator. Data is written into a memory in sequential order, and then read out using addresses specified by the PN state generator. To deinterleave, the interleaved data is written into a memory using addresses specified by the PN state generator, and then read out in sequential order. A set of PN state generators that provide excellent coding performance is provided.

Abstract: A counter for synthesizing clock signals with minimal jitter. The inventive counter has a first counter stage; a look-ahead circuit input connected to said first counter stage; and a selection circuit for choosing between an output of said first counter stage and an output of said look-ahead circuit as an output of said counter. In the specific embodiment, the first counter stage is adapted to receive a first clock signal having a frequency of N cycles per second and output a second clock signal having a frequency of M cycles per second. The first counter stage includes an accumulator having a rollover point at which an instantaneous count thereof exceeds the value of N−M. The look-ahead circuit determines for a present clock cycle the rollover point for a preceding clock cycle. The look-ahead circuit is a second counter stage adapted to ascertain whether the rising edge or the trailing edge of the second clock signal is closer to the rollover point and output an indication with respect thereto.

Abstract: The present invention is a novel and improved technique for decoding technique with particular application to turbo, or iterative, coding techniques. In accordance with one embodiment of the invention, a system for decoding includes a channel deinterleaver RAM for storing a block of symbol estimates, a set of S state metric calculators. Each state metric calculator is for generating a set of state metric calculations and a set of S+1 window RAMs, wherein, S of said S+1 window RAMs provide symbol estimates to said S state metric calculators. A remaining window RAM receives symbol estimates from said channel deinterleaver RAM.

Abstract: An interleaver that implements the LCS turbo interleaver algorithm utilized by the CDMA2000 standard is described. The interleaver includes a first computation unit for receiving an input address and computing a first sequential interleaved address during a first clock cycle in response thereto. A second computation unit is included for receiving an input address and computing a second sequential interleaved address during the first clock cycle in response thereto. The interleaver further includes a comparator for determining whether the first or the second sequential interleaved address is invalid and generating a signal in response thereto. The output of the comparator provides a control signal to a switch which selects the first or the second sequential interleaved address as an output interleaved address for the first clock cycle. The interleaver is further designed to move in a forward direction or a reverse direction.