Patents by Inventor Steven J. Ratner

Steven J. Ratner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6678130
    Abstract: An electronic circuit consists of a voltage regulator and an electrostatic discharge (ESD) shunt. The voltage regulator maintains a prescribed voltage for the voltage supply of the chip. The ESD shunt protects the chip circuitry from undesirable levels of current or voltage. The voltage regulator and the ESD shunt share the functionality of a single, very large transistor. This combination results in a circuit with a smaller area, much smaller than if the two circuits had been built separately. With the reduction in area, both circuits can be manufactured on a single chip.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: January 13, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Steven J. Ratner, Hyoung Jo Youn, Leandro A. Chua, Jr.
  • Publication number: 20020171984
    Abstract: An electronic circuit consists of a voltage regulator and an electrostatic discharge (ESD) shunt. The voltage regulator maintains a prescribed voltage for the voltage supply of the chip. The ESD shunt protects the chip circuitry from undesirable levels of current or voltage. The voltage regulator and the ESD shunt share the functionality of a single, very large transistor. This combination results in a circuit with a smaller area, much smaller than if the two circuits had been built separately. With the reduction in area, both circuits can be manufactured on a single chip.
    Type: Application
    Filed: March 27, 2001
    Publication date: November 21, 2002
    Inventors: Steven J. Ratner, Hyoung Jo Youn, Leandro A. Chua
  • Patent number: 5726587
    Abstract: An improved tri-state output buffer having an emitter-follower output stage clamps the reverse-bias voltage across the base-emitter path of an emitter-follower to limit the output leakage current and thereby extending the operating life of an integrated circuit (IC). A current sensitive voltage device such as a bipolar transistor or diode clamps the reverse-bias voltage of the base-emitter path. Voltage clamping prevents the bipolar transistors from activating while the buffer is disabled. The output leakage current that occurs when the junction is forward biased is minimized. This results in low output load capacitance that improves the propagation delay particularly when multiple buffers are used.
    Type: Grant
    Filed: September 3, 1996
    Date of Patent: March 10, 1998
    Assignee: Hewlett-Packard Company
    Inventor: Steven J. Ratner
  • Patent number: 5506535
    Abstract: An I/O circuit that provides bidirectional signal access to an integrated circuit (IC) core has voltage transformation capability to manage different voltage requirements. Although the I/O circuit and the core are fabricated from the same IC process, the I/O circuit can operate at non-process constrained voltages. The I/O circuit provides an output signal at the necessary voltage level to drive a component in the discrete environment while limiting the voltage supplied to the IC core to the maximum device voltage defined by the selected process.
    Type: Grant
    Filed: July 28, 1994
    Date of Patent: April 9, 1996
    Assignee: Hewlett-Packard Company
    Inventor: Steven J. Ratner