Abstract: A system may comprise multiple master/slave devices coupled to a common bus, where one of the devices may operate as the current master device and the other devices may operate as current slave devices. Current slave devices may embed bus ownership request information within response packets transmitted in response to standard bus operations, such as reads and writes, issued by the current master device. When the current master device is idle, its bus interface may continually poll the current slave devices at regular intervals, according to a specified protocol, to ascertain whether any of them are requesting bus ownership. A response to a request for bus ownership received by the current master device may be configured according to desired system functionality. In one system, ownership may always be transferred to the requesting device.

Abstract: A computer system, more generally a master-slave system, may be configured with interrupt handling capability without additional dedicated interrupt lines. An interrupt condition may be bound with its relevant cause information and transmitted by a slave device during a typical response to any operation that a master device may have issued, such as a read or a write. In addition, a link level protocol may be configured in the bus interface of the master device to continually poll specified addresses, or to issue a unique command targeted at interrupts. The master device may be unaware of the unique requests, as the bus may remain idle as seen by the master device. The response to the unique requests may be similar to the interrupt message information transmitted as part of a response to a standard request that may be made by the master device.

Abstract: A data signal receiver (100) forms line samples of a received modulated data signal and applies them to a fractionally spaced equalizer (150). The equalizer outputs are demodulated and decisions are formed as to the values of the transmitted data symbols. The equalizer itself is comprised of a plurality of equalizer sections (220, 240, 260, 280) each of which multiplies ones of the line samples with respective ones of a queue of coefficients to form a partial sum. The partial sums are combined to form the overall equalizer output. Timing recovery and tap rotation control signals generated within the equalizer are generated as a function of the location within the coefficient queue of a reference coefficient, the latter illustratively being the coefficient of largest complex magnitude. An arbitration circuit (680) within each equalizer section determines whether that section holds the reference coefficient.