Patents by Inventor Steven Jaloviar

Steven Jaloviar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Replacement gate structures for advanced integrated circuit structure fabrication
    Patent number: 11482611
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: October 25, 2022
    Assignee: Intel Corporation
    Inventors: Byron Ho, Steven Jaloviar, Jeffrey S. Leib, Michael L. Hattendorf, Christopher P. Auth
  • REPLACEMENT GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
    Publication number: 20210091206
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.
    Type: Application
    Filed: November 20, 2020
    Publication date: March 25, 2021
    Inventors: Byron HO, Steven JALOVIAR, Jeffrey S. LEIB, Michael L. HATTENDORF, Christopher P. AUTH
  • Replacement gate structures for advanced integrated circuit structure fabrication
    Patent number: 10886383
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Byron Ho, Steven Jaloviar, Jeffrey S. Leib, Michael L. Hattendorf, Christopher P. Auth
  • REPLACEMENT GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
    Publication number: 20200388697
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Byron HO, Steven JALOVIAR, Jeffrey S. LEIB, Michael L. HATTENDORF, Christopher P. AUTH
  • Replacement gate structures for advanced integrated circuit structure fabrication
    Patent number: 10790378
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: Byron Ho, Steven Jaloviar, Jeffrey S. Leib, Michael L. Hattendorf, Christopher P. Auth
  • REPLACEMENT GATE STRUCTURES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
    Publication number: 20190165146
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.
    Type: Application
    Filed: October 25, 2018
    Publication date: May 30, 2019
    Inventors: Byron HO, Steven JALOVIAR, Jeffrey S. LEIB, Michael L. HATTENDORF, Christopher P. AUTH
  • Replacement gate structures for advanced integrated circuit structure fabrication
    Patent number: 10121875
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: Byron Ho, Steven Jaloviar, Jeffrey S. Leib, Michael L. Hattendorf, Christopher P. Auth