Patents by Inventor Steven James Dillen
Steven James Dillen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9685940Abstract: Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.Type: GrantFiled: August 4, 2015Date of Patent: June 20, 2017Assignee: QUALCOMM IncorporatedInventors: Ramaprasath Vilangudipitchai, Dorav Kumar, Steven James Dillen, Ohsang Kwon, Javid Jaffari
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Patent number: 9678154Abstract: In one embodiment, a method for signal delay in a scan path comprises, in a scan mode, delaying a scan signal in the scan path by propagating the scan signal through a plurality of delay devices coupled in series, wherein a first one of the delay devices is powered by a first voltage, a second one of the delay devices is powered by a second voltage, and the second voltage is greater than the first voltage. The method also comprises, in a functional mode, disabling the delay devices.Type: GrantFiled: October 30, 2014Date of Patent: June 13, 2017Assignee: QUALCOMM IncorporatedInventors: Animesh Datta, Qi Ye, Steven James Dillen
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Patent number: 9584121Abstract: A MOS device includes a first latch configured with one latch feedback F and configured to receive a latch input I and a latch clock C. The first latch is configured to output Q, where the output Q is a function of CF, IF, and IC, and the latch feedback F is a function of the output Q. The first latch may include a first set of transistors stacked in series in which the first set of transistors includes at least five transistors. The MOS device may further include a second latch coupled to the first latch. The second latch may be configured as a latch in a scan mode and as a pulse latch in a functional mode. The first latch may operate as a master latch and the second latch may operate as a slave latch during the scan mode.Type: GrantFiled: June 10, 2015Date of Patent: February 28, 2017Assignee: QUALCOMM INCORPORATEDInventors: Qi Ye, Zhengyu Duan, Steven James Dillen, Animesh Datta
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Patent number: 9577635Abstract: A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ?C, where E is the internal enable node and C is the clock.Type: GrantFiled: January 15, 2015Date of Patent: February 21, 2017Assignee: QUALCOMM INCORPORATEDInventors: Seid Hadi Rasouli, Steven James Dillen, Animesh Datta
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Patent number: 9564881Abstract: A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionally I1IA at a delay module output, where I1 is a function of I and IA is a function of IN0 and B0, and where I is a delay module input, B0 is a first input bit, and IN0 is a first net input.Type: GrantFiled: May 22, 2015Date of Patent: February 7, 2017Assignee: QUALCOMM INCORPORATEDInventors: Qi Ye, Steven James Dillen, Animesh Datta, Zhengyu Duan, Satyanarayana Sahu, Praveen Narendranath
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Publication number: 20160365856Abstract: A MOS device includes a first latch configured with one latch feedback F and configured to receive a latch input I and a latch clock C. The first latch is configured to output Q, where the output Q is a function of CF, IF, and IC, and the latch feedback F is a function of the output Q. The first latch may include a first set of transistors stacked in series in which the first set of transistors includes at least five transistors. The MOS device may further include a second latch coupled to the first latch. The second latch may be configured as a latch in a scan mode and as a pulse latch in a functional mode. The first latch may operate as a master latch and the second latch may operate as a slave latch during the scan mode.Type: ApplicationFiled: June 10, 2015Publication date: December 15, 2016Inventors: Qi YE, Zhengyu DUAN, Steven James DILLEN, Animesh DATTA
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Publication number: 20160344374Abstract: A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionally I1IA at a delay module output, where I1 is a function of I and IA is a function of IN0 and B0, and where I is a delay module input, B0 is a first input bit, and IN0 is a first net input.Type: ApplicationFiled: May 22, 2015Publication date: November 24, 2016Inventors: Qi YE, Steven James DILLEN, Animesh DATTA, Zhengyu DUAN, Satyanarayana SAHU, Praveen NARENDRANATH
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Publication number: 20160248414Abstract: Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.Type: ApplicationFiled: August 4, 2015Publication date: August 25, 2016Inventors: Ramaprasath Vilangudipitchai, Dorav Kumar, Steven James Dillen, Ohsang Kwon, Javid Jaffari
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Publication number: 20160211846Abstract: A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ?C, where E is the internal enable node and C is the clock.Type: ApplicationFiled: January 15, 2015Publication date: July 21, 2016Inventors: Seid Hadi RASOULI, Steven James DILLEN, Animesh DATTA
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Publication number: 20160124043Abstract: In one embodiment, a method for signal delay in a scan path comprises, in a scan mode, delaying a scan signal in the scan path by propagating the scan signal through a plurality of delay devices coupled in series, wherein a first one of the delay devices is powered by a first voltage, a second one of the delay devices is powered by a second voltage, and the second voltage is greater than the first voltage. The method also comprises, in a functional mode, disabling the delay devices.Type: ApplicationFiled: October 30, 2014Publication date: May 5, 2016Inventors: Animesh Datta, Qi Ye, Steven James Dillen