Abstract: A cache system, having: a first cache set; a second cache set; and a logic circuit coupled to a processor to control the caches based on at least respective first and second registers. When a connection to an address bus receives a memory address from the processor, the logic circuit is configured to: generate a set index from at least the address; and determine whether the generated set index matches with a content stored in the first register or with a content stored in the second register. And, the logic circuit is configured to implement a command via the first cache set in response to the generated set index matching with the content stored in the first register and via the second cache set in response to the generated set index matching with the content stored in the second register.

Abstract: Methods, systems, and apparatuses related to re-order buffers and for protection from timing-based security attacks are described. A processor may have functional units configured to execute instructions out of order, a re-order buffer configured to buffer the execution results of instructions for output in order, and a controller configured to randomize data timing in the re-order buffer. For example, the controller can make random adjustments to the capacity of the re-order buffer in buffering and/or sorting execution results and thus randomize data timing in the re-order buffer.

Abstract: Disclosed herein are vector index registers for storing or loading indexes of true and/or false results of conditional operations in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors in various types of operations.

Abstract: A method performed in a processor, includes: receiving, in the processor, a branch instruction in the processing; determining, by the processor, an address of an instruction after the branch instruction as a candidate for speculative execution, the address including an object identification and an offset; and determining, by the processor, whether or not to perform speculative execution of the instruction after the branch instruction based on the object identification of the address.

Abstract: A cache system having cache sets, registers associated with the cache sets respectively, and a logic circuit coupled to a processor to control the cache sets according to the registers. When a connection to an address bus of the system receives a memory address from the processor, the logic circuit can be configured to: generate an extended tag from at least the memory address; and determine whether the generated extended tag matches with a first extended tag for a first cache set or a second extended tag for a second cache set of the system. Also, the logic circuit can also be configured to implement a command received from the processor via the first cache set in response to the generated extended tag matching with the first extended tag and via the second cache set in response to the generated extended tag matching with the second extended tag.

Abstract: A computer system having an address system of a first predetermined width in which each address of the first predetermined width in the address system includes a first portion identifying an object and a second portion identifying an offset relative to the object, where a static identifier for the first portion is predetermined to identify an address space having a second predetermined width that is smaller than the first predetermined width, or a space of kernel objects.

Abstract: A cache system, having a first cache, a second cache, and a logic circuit coupled to control the first cache and the second cache according to an execution type of a processor. When an execution type of a processor is a first type indicating non-speculative execution of instructions and the first cache is configured to service commands from a command bus for accessing a memory system, the logic circuit is configured to copy a portion of content cached in the first cache to the second cache. The cache system can include a configurable data bit. The logic circuit can be coupled to control the caches according to the bit. Alternatively, the caches can include cache sets. The caches can also include registers associated with the cache sets respectively. The logic circuit can be coupled to control the cache sets according to the registers.

Abstract: Disclosed herein are vector index registers in vector processors that each store multiple addresses for accessing multiple positions in vectors. It is known to use scalar index registers in vector processors to access multiple positions of vectors by changing the scalar index registers in vector operations. By using a vector indexing register for indexing positions of one or more operand vectors, the scalar index register can be replaced and at least the continual changing of the scalar index register can be avoided.

Abstract: Disclosed herein are vector index registers for storing or loading indexes of true and/or false results of conditional operations using multiple lane processing in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors in various types of operations that can leverage multi-lane processing.

Abstract: A computing system, method and apparatus to cache a portion of a data block. A processor can access data using memory addresses in an address space. A first memory can store a block of data at a block of contiguous addresses in the space of memory address. A second memory can cache a first portion of the block of data identified by an item selection vector. For example, response to a request to cache the block of data stored in the first memory, the computing system can communicate the first portion of the block of data from the first memory to the second memory according to the item selection vector without accessing a second portion of the block of data. Thus, different data blocks in the first memory of a same size can be each cached in different cache blocks of different sizes in the second memory.

Abstract: A method performed in a processor, includes: receiving, in the processor, a branch instruction in the processing; determining, by the processor, an address of an instruction after the branch instruction as a candidate for speculative execution, the address including an object identification and an offset; and determining, by the processor, whether or not to perform speculative execution of the instruction after the branch instruction based on the object identification of the address.

Abstract: A cache system, having: a first cache; a second cache; a configurable data bit; and a logic circuit coupled to a processor to control the caches based on the configurable bit. When the configurable bit is in a first state, the logic circuit is configured to: implement commands for accessing a memory system via the first cache, when an execution type is a first type; and implement commands for accessing the memory system via the second cache, when the execution type is a second type. When the configurable data bit is in a second state, the logic circuit is configured to: implement commands for accessing the memory system via the second cache, when the execution type is the first type; and implement commands for accessing the memory system via the first cache, when the execution type is the second type.

Abstract: A cache system having cache sets, and the cache sets having a first cache set configured to provide a first physical output upon a cache hit and a second cache set configured to provide a second physical output upon a cache hit. The cache system also has a control register and a mapping circuit coupled to the control register to map respective physical outputs of the cache sets to a first logical cache and a second logical cache according to a state of the control register. The first logical cache can be a normal or main cache for non-speculative executions by a processor and the second logical cache can be a shadow cache for speculative executions by the processor.

Abstract: A computer system having an address system of a first predetermined width in which each address of the first predetermined width in the address system includes a first portion identifying an object and a second portion identifying an offset relative to the object, where a static identifier for the first portion is predetermined to identify an address space having a second predetermined width that is smaller than the first predetermined width, or a space of kernel objects.

Abstract: Systems, apparatuses, and methods related to securing domain crossing using domain access tables are described. For example, a computer processor can have registers configured to store locations of domain access tables respectively for predefined, non-hierarchical domains. Each respective domain access table can be pre-associated with a respective domain and can have entries configured to identify entry points of the respective domain. The processor is configured to enforce domain crossing in instruction execution using the domain access tables and to prevent arbitrary and/or unauthorized domain crossing.

Abstract: A computing system, method and apparatus to cache a portion of a data block. A processor can access data using memory addresses in an address space. A first memory can store a block of data at a block of contiguous addresses in the space of memory address. A second memory can cache a first portion of the block of data identified by an item selection vector. For example, response to a request to cache the block of data stored in the first memory, the computing system can communicate the first portion of the block of data from the first memory to the second memory according to the item selection vector without accessing a second portion of the block of data. Thus, different data blocks in the first memory of a same size can be each cached in different cache blocks of different sizes in the second memory.

Abstract: A cache system, having: a first cache; a second cache; a configurable data bit; and a logic circuit coupled to a processor to control the caches based on the configurable bit. When the configurable bit is in a first state, the logic circuit is configured to: implement commands for accessing a memory system via the first cache, when an execution type is a first type; and implement commands for accessing the memory system via the second cache, when the execution type is a second type. When the configurable data bit is in a second state, the logic circuit is configured to: implement commands for accessing the memory system via the second cache, when the execution type is the first type; and implement commands for accessing the memory system via the first cache, when the execution type is the second type.

Abstract: A cache system having cache sets, and the cache sets having a first cache set configured to provide a first physical output upon a cache hit and a second cache set configured to provide a second physical output upon a cache hit. The cache system also has a control register and a mapping circuit coupled to the control register to map respective physical outputs of the cache sets to a first logical cache and a second logical cache according to a state of the control register. The first logical cache can be a normal or main cache for non-speculative executions by a processor and the second logical cache can be a shadow cache for speculative executions by the processor.

Abstract: Methods, systems, and apparatuses related to adjustable security levels in processors are described. A processor may have functional units and a register configured to control security operations of the functional units. The register configures the functional units to operate in a first mode of security operations when the register contains a first setting; and the register configures the functional units to operate in a second mode of security operations when the register contains a second setting (e.g., to skip/bypassing a set of security operation circuit for enhanced execution speed).

Abstract: Systems, apparatuses, and methods related to securing domain crossing using domain access tables are described. For example, a computer processor can have registers configured to store locations of domain access tables respectively for predefined, non-hierarchical domains. Each respective domain access table can be pre-associated with a respective domain and can have entries configured to identify entry points of the respective domain. The processor is configured to enforce domain crossing in instruction execution using the domain access tables and to prevent arbitrary and/or unauthorized domain crossing.