Abstract: A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

Abstract: A design structure is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.

Abstract: A method for implementing phase rotator circuits and phase rotator circuit of the invention includes a polyphase filter network to create a quadrature phase version of the input signal. The polyphase filter network is partitioned into a first part that is physically isolated from the phase rotator circuit and a second part that is embedded in the phase rotator circuit. The second part of the polyphase filter is coupled to the first part of the polyphase filter by a high-pass equalizing buffer stage. The second part of the polyphase filter is coupled to the phase rotator circuit by a bandlimiting buffer stage.

Abstract: An apparatus and method is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.

Abstract: A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

Abstract: A method and apparatus to equalize currents on a matching pair of FETs having sources connected together on a silicon on insulator semiconductor chip, or other chip wherein FET bodies can be individually biased. During a determination period, functional inputs coupled to the gates of the matching pair of FETs are short circuited, and a DAC adjusts a first body voltage of a first FET in the matching pair of FETs relative to a second body voltage of a second FET in the matching pair of FETs until a currents in the first FET and the second FET are equal, within resolution of the DAC's voltage granularity. A proper DAC control value is stored and applied to the DAC following the determination period when the short circuit is removed from the functional inputs.

Abstract: A design structure comprising apparatus to equalize currents on a matching pair of FETs having sources connected together on a silicon on insulator semiconductor chip, or other chip wherein FET bodies can be individually biased. During a determination period, functional inputs coupled to the gates of the matching pair of FETs are short circuited, and a DAC adjusts a first body voltage of a first FET in the matching pair of FETs relative to a second body voltage of a second FET in the matching pair of FETs until a currents in the first FET and the second FET are equal, within resolution of the DAC's voltage granularity. A proper DAC control value is stored and applied to the DAC following the determination period when the short circuit is removed from the functional inputs.

Abstract: A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

Abstract: A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.

Abstract: An apparatus and method is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.

Abstract: A method for implementing phase rotator circuits and phase rotator circuit of the invention includes a polyphase filter network to create a quadrature phase version of the input signal. The polyphase filter network is partitioned into a first part that is physically isolated from the phase rotator circuit and a second part that is embedded in the phase rotator circuit. The second part of the polyphase filter is coupled to the first part of the polyphase filter by a high-pass equalizing buffer stage. The second part of the polyphase filter is coupled to the phase rotator circuit by a bandlimiting buffer stage.

Abstract: An arrangement to enable automatic baud rate speed negotiation between transceivers having different operating speed characteristics is implemented. When an event indicative of a possible baud rate mismatch occurs, control signals are generated and used to trigger a baud rate negotiation procedure. In the baud rate negotiation procedure, a predetermined pattern is transmitted, the baud rate of the respective transmitting transceiver is decoded, and the decoded baud rate is used to select an appropriate filtering for the transceiver.

Abstract: A design structure is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.

Abstract: An arrangement to enable automatic baud rate speed negotiation between transceivers having different operating speed characteristics is implemented. When an event indicative of a possible baud rate mismatch occurs, control signals are generated and used to trigger a baud rate negotiation procedure. In the baud rate negotiation procedure, a predetermined pattern is transmitted, the baud rate of the respective transmitting transceiver is decoded, and the decoded baud rate is used to select an appropriate filtering for the transceiver.

Abstract: An optical margin testing system is provided for automatic power control loops. An optical circuit includes a laser diode and a monitor diode coupled to the automatic power control loop. A bias generator circuit generates a control signal. The control signal is applied to the automatic power control loop. The control signal enables an operation point of the laser diode to both increase and decrease by a set percentage value for optical margin testing. The bias generator circuit includes a tri-state receiver. An input signal is applied to the tri-state receiver for selecting one of a normal operational mode, an increased set percentage value operational mode, and a decreased set percentage value operational mode. A current mirror is coupled to the tri-state receiver provides the control signal that is applied to the automatic power control loop.

Abstract: An arrangement to enable automatic baud rate speed negotiation between transceivers having different operating speed characteristics is implemented. When an event indicative of a possible baud rate mismatch occurs, control signals are generated and used to trigger a baud rate negotiation procedure. In the baud rate negotiation procedure, a predetermined pattern is transmitted, the baud rate of the respective transmitting transceiver is decoded, and the decoded baud rate is used to select an appropriate filtering for the transceiver.

Abstract: An arrangement to enable automatic baud rate speed negotiation between transceivers having different operating speed characteristics is implemented. When an event indicative of a possible baud rate mismatch occurs, control signals are generated and used to trigger a baud rate negotiation procedure. In the baud rate negotiation procedure, a predetermined pattern is transmitted, the baud rate of the respective transmitting transceiver is decoded, and the decoded baud rate is used to select an appropriate filtering for the transceiver.

Abstract: A method and apparatus are provided to ensure that laser optical power does not exceed a “safe” level in an open loop parallel optical link in the event that a fiber optic ribbon cable is broken or otherwise severed. A duplex parallel optical link includes a transmitter and receiver pair and a fiber optic ribbon that includes a designated number of channels that cannot be split. The duplex transceiver includes a corresponding transmitter and receiver that are physically attached to each other and cannot be detached therefrom, so as to ensure safe, laser optical power in the event that the fiber optic ribbon cable is broken or severed. Safe optical power is ensured by redundant current and voltage safety checks.

Abstract: An optical margin testing system is provided for automatic power control loops. An optical circuit includes a laser diode and a monitor diode coupled to the automatic power control loop. A bias generator circuit generates a control signal. The control signal is applied to the automatic power control loop. The control signal enables an operation point of the laser diode to both increase and decrease by a set percentage value for optical margin testing. The bias generator circuit includes a tri-state receiver. An input signal is applied to the tri-state receiver for selecting one of a normal operational mode, an increased set percentage value operational mode, and a decreased set percentage value operational mode. A current mirror is coupled to the tri-state receiver provides the control signal that is applied to the automatic power control loop.

Abstract: A laser driver, e.g., a vertical cavity surface emitting laser (VCSEL) driver, with low duty cycle distortion is provided. An fT doubler circuit, used as the driver input, has two current sources, and reduces parasitic capacitance which can cause duty cycle distortion. The current sources may be analog or digital sources, the latter being digitally adjustable to provide for digital modulation adjustment. A current mirror circuit with a reference current source is provided for the two current sources.