Patents by Inventor Steven John Baumgartner

Steven John Baumgartner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7945805
    Abstract: A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: May 17, 2011
    Assignee: International Business Machines Corporation
    Inventors: Steven John Baumgartner, Anthony Richard Bonaccio, Timothy Clyde Buchholtz, Daniel Mark Dreps, Charles Porter Geer, Mounir Meghelli, Sergey Vladimirovich Rylov, David W. Siljenberg, Dana Marie Woeste
  • Patent number: 7904741
    Abstract: A design structure is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: March 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Steven John Baumgartner, Charles Porter Geer
  • Patent number: 7733984
    Abstract: A method for implementing phase rotator circuits and phase rotator circuit of the invention includes a polyphase filter network to create a quadrature phase version of the input signal. The polyphase filter network is partitioned into a first part that is physically isolated from the phase rotator circuit and a second part that is embedded in the phase rotator circuit. The second part of the polyphase filter is coupled to the first part of the polyphase filter by a high-pass equalizing buffer stage. The second part of the polyphase filter is coupled to the phase rotator circuit by a bandlimiting buffer stage.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: June 8, 2010
    Assignee: International Business Machines Corporation
    Inventors: Steven John Baumgartner, Anthony Richard Bonaccio, John Francis Bulzacchelli, Daniel Mark Dreps
  • Patent number: 7716514
    Abstract: An apparatus and method is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: May 11, 2010
    Assignee: International Business Machines Corporation
    Inventors: Steven John Baumgartner, Charles Porter Geer
  • Patent number: 7624297
    Abstract: A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: November 24, 2009
    Assignee: International Business Machines Corporation
    Inventors: Steven John Baumgartner, Anthony Richard Bonaccio, Timothy Clyde Buchholtz, Daniel Mark Dreps, Charles Porter Geer, Mounir Meghelli, Sergey Vladimirovich Rylov, David W. Siljenberg, Dana Marie Woeste
  • Publication number: 20090189671
    Abstract: A method and apparatus to equalize currents on a matching pair of FETs having sources connected together on a silicon on insulator semiconductor chip, or other chip wherein FET bodies can be individually biased. During a determination period, functional inputs coupled to the gates of the matching pair of FETs are short circuited, and a DAC adjusts a first body voltage of a first FET in the matching pair of FETs relative to a second body voltage of a second FET in the matching pair of FETs until a currents in the first FET and the second FET are equal, within resolution of the DAC's voltage granularity. A proper DAC control value is stored and applied to the DAC following the determination period when the short circuit is removed from the functional inputs.
    Type: Application
    Filed: January 25, 2008
    Publication date: July 30, 2009
    Inventors: Steven John Baumgartner, David W. Siljenberg, Dana Marie Woeste
  • Publication number: 20090193372
    Abstract: A design structure comprising apparatus to equalize currents on a matching pair of FETs having sources connected together on a silicon on insulator semiconductor chip, or other chip wherein FET bodies can be individually biased. During a determination period, functional inputs coupled to the gates of the matching pair of FETs are short circuited, and a DAC adjusts a first body voltage of a first FET in the matching pair of FETs relative to a second body voltage of a second FET in the matching pair of FETs until a currents in the first FET and the second FET are equal, within resolution of the DAC's voltage granularity. A proper DAC control value is stored and applied to the DAC following the determination period when the short circuit is removed from the functional inputs.
    Type: Application
    Filed: January 25, 2008
    Publication date: July 30, 2009
    Inventors: Steven John Baumgartner, David W. Siljenberg, Dana Marie Woeste
  • Publication number: 20080148088
    Abstract: A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.
    Type: Application
    Filed: October 31, 2007
    Publication date: June 19, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven John Baumgartner, Anthony Richard Bonaccio, Timothy Clyde Buchholtz, Daniel Mark Dreps, Charles Porter Geer, Mounir Meghelli, Sergey Vladimirovich Rylov, David W. Siljenberg, Dana Marie Woeste
  • Publication number: 20080147952
    Abstract: A high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.
    Type: Application
    Filed: December 13, 2006
    Publication date: June 19, 2008
    Inventors: Steven John Baumgartner, Anthony Richard Bonaccio, Timothy Clyde Buchholtz, Daniel Mark Dreps, Charles Porter Geer, Mounir Meghelli, Sergey Vladimirovich Rylov, David W. Siljenberg, Dana Marie Woeste
  • Publication number: 20080126566
    Abstract: An apparatus and method is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.
    Type: Application
    Filed: September 19, 2006
    Publication date: May 29, 2008
    Inventors: Steven John Baumgartner, Charles Porter Geer
  • Publication number: 20080107212
    Abstract: A method for implementing phase rotator circuits and phase rotator circuit of the invention includes a polyphase filter network to create a quadrature phase version of the input signal. The polyphase filter network is partitioned into a first part that is physically isolated from the phase rotator circuit and a second part that is embedded in the phase rotator circuit. The second part of the polyphase filter is coupled to the first part of the polyphase filter by a high-pass equalizing buffer stage. The second part of the polyphase filter is coupled to the phase rotator circuit by a bandlimiting buffer stage.
    Type: Application
    Filed: November 8, 2006
    Publication date: May 8, 2008
    Inventors: Steven John Baumgartner, Anthony Richard Bonaccio, John Francis Bulzacchelli, Daniel Mark Dreps
  • Patent number: 7359432
    Abstract: An arrangement to enable automatic baud rate speed negotiation between transceivers having different operating speed characteristics is implemented. When an event indicative of a possible baud rate mismatch occurs, control signals are generated and used to trigger a baud rate negotiation procedure. In the baud rate negotiation procedure, a predetermined pattern is transmitted, the baud rate of the respective transmitting transceiver is decoded, and the decoded baud rate is used to select an appropriate filtering for the transceiver.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: April 15, 2008
    Assignee: International Business Machines Corporation
    Inventor: Steven John Baumgartner
  • Publication number: 20080072093
    Abstract: A design structure is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.
    Type: Application
    Filed: October 11, 2007
    Publication date: March 20, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven John Baumgartner, Charles Porter Geer
  • Patent number: 7212589
    Abstract: An arrangement to enable automatic baud rate speed negotiation between transceivers having different operating speed characteristics is implemented. When an event indicative of a possible baud rate mismatch occurs, control signals are generated and used to trigger a baud rate negotiation procedure. In the baud rate negotiation procedure, a predetermined pattern is transmitted, the baud rate of the respective transmitting transceiver is decoded, and the decoded baud rate is used to select an appropriate filtering for the transceiver.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: May 1, 2007
    Assignee: International Business Machines Corporation
    Inventor: Steven John Baumgartner
  • Patent number: 6870864
    Abstract: An optical margin testing system is provided for automatic power control loops. An optical circuit includes a laser diode and a monitor diode coupled to the automatic power control loop. A bias generator circuit generates a control signal. The control signal is applied to the automatic power control loop. The control signal enables an operation point of the laser diode to both increase and decrease by a set percentage value for optical margin testing. The bias generator circuit includes a tri-state receiver. An input signal is applied to the tri-state receiver for selecting one of a normal operational mode, an increased set percentage value operational mode, and a decreased set percentage value operational mode. A current mirror is coupled to the tri-state receiver provides the control signal that is applied to the automatic power control loop.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: March 22, 2005
    Assignee: International Business Machines Corporation
    Inventor: Steven John Baumgartner
  • Patent number: 6771694
    Abstract: An arrangement to enable automatic baud rate speed negotiation between transceivers having different operating speed characteristics is implemented. When an event indicative of a possible baud rate mismatch occurs, control signals are generated and used to trigger a baud rate negotiation procedure. In the baud rate negotiation procedure, a predetermined pattern is transmitted, the baud rate of the respective transmitting transceiver is decoded, and the decoded baud rate is used to select an appropriate filtering for the transceiver.
    Type: Grant
    Filed: July 12, 2000
    Date of Patent: August 3, 2004
    Assignee: International Business Machines Corporation
    Inventor: Steven John Baumgartner
  • Publication number: 20040022306
    Abstract: An arrangement to enable automatic baud rate speed negotiation between transceivers having different operating speed characteristics is implemented. When an event indicative of a possible baud rate mismatch occurs, control signals are generated and used to trigger a baud rate negotiation procedure. In the baud rate negotiation procedure, a predetermined pattern is transmitted, the baud rate of the respective transmitting transceiver is decoded, and the decoded baud rate is used to select an appropriate filtering for the transceiver.
    Type: Application
    Filed: July 31, 2003
    Publication date: February 5, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Steven John Baumgartner
  • Patent number: 6658030
    Abstract: A method and apparatus are provided to ensure that laser optical power does not exceed a “safe” level in an open loop parallel optical link in the event that a fiber optic ribbon cable is broken or otherwise severed. A duplex parallel optical link includes a transmitter and receiver pair and a fiber optic ribbon that includes a designated number of channels that cannot be split. The duplex transceiver includes a corresponding transmitter and receiver that are physically attached to each other and cannot be detached therefrom, so as to ensure safe, laser optical power in the event that the fiber optic ribbon cable is broken or severed. Safe optical power is ensured by redundant current and voltage safety checks.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: December 2, 2003
    Assignee: International Business Machines Corporation
    Inventors: Steven John Baumgartner, Daniel Scott Hedin, Matthew James Paschal
  • Publication number: 20030142707
    Abstract: An optical margin testing system is provided for automatic power control loops. An optical circuit includes a laser diode and a monitor diode coupled to the automatic power control loop. A bias generator circuit generates a control signal. The control signal is applied to the automatic power control loop. The control signal enables an operation point of the laser diode to both increase and decrease by a set percentage value for optical margin testing. The bias generator circuit includes a tri-state receiver. An input signal is applied to the tri-state receiver for selecting one of a normal operational mode, an increased set percentage value operational mode, and a decreased set percentage value operational mode. A current mirror is coupled to the tri-state receiver provides the control signal that is applied to the automatic power control loop.
    Type: Application
    Filed: January 28, 2002
    Publication date: July 31, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Steven John Baumgartner
  • Patent number: 6532245
    Abstract: A laser driver, e.g., a vertical cavity surface emitting laser (VCSEL) driver, with low duty cycle distortion is provided. An fT doubler circuit, used as the driver input, has two current sources, and reduces parasitic capacitance which can cause duty cycle distortion. The current sources may be analog or digital sources, the latter being digitally adjustable to provide for digital modulation adjustment. A current mirror circuit with a reference current source is provided for the two current sources.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: March 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: Matthew James Paschal, Steven John Baumgartner