Abstract: A semiconductor device is provided, the semiconductor device comprising a substrate and a first semiconductor fin and a second semiconductor fin disposed over the substrate. The first and second semiconductor fins each having an upper portion and a width. Epitaxial structures are disposed over the upper portions of the first and second semiconductor fins. The upper portions of the first and second semiconductor fins and the epitaxial structures provide an active layer. A metal structure is positioned between the active layer and the substrate. The metal structure extends at least across the widths of the first and second semiconductor fins and a separation distance between the fins. A first isolation material separates the metal structure from the active layer. A second isolation material separates the metal structure from the substrate. A contact electrically connects the metal structure to the epitaxial structures.

Abstract: A semiconductor device is provided, the semiconductor device comprising a substrate and a first semiconductor fin and a second semiconductor fin disposed over the substrate. The first and second semiconductor fins each having an upper portion and a width. Epitaxial structures are disposed over the upper portions of the first and second semiconductor fins. The upper portions of the first and second semiconductor fins and the epitaxial structures provide an active layer. A metal structure is positioned between the active layer and the substrate. The metal structure extends at least across the widths of the first and second semiconductor fins and a separation distance between the fins. A first isolation material separates the metal structure from the active layer. A second isolation material separates the metal structure from the substrate. A contact electrically connects the metal structure to the epitaxial structures.

Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.

Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.

Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.

Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

Abstract: A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor structure, the structure including a semiconductor substrate having a n-type device region and a p-type device region, the p-type device region including an upper layer of p-type semiconductor material, a hard mask layer over both regions, and a mask over the structure for patterning at least one fin in each region. The method further includes creating partial fin(s) in each region from the starting semiconductor structure, creating a conformal liner over the structure, creating a punch-through-stop (PTS) in each region, causing each PTS to diffuse across a top portion of the substrate, and creating full fin(s) in each region from the partial fin(s).

Abstract: Methods for self-aligned gate-first VFETs using gate-spacer recess and the resulting devices are disclosed.

Abstract: A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor structure, the structure including a semiconductor substrate having a n-type device region and a p-type device region, the p-type device region including an upper layer of p-type semiconductor material, a hard mask layer over both regions, and a mask over the structure for patterning at least one fin in each region. The method further includes creating partial fin(s) in each region from the starting semiconductor structure, creating a conformal liner over the structure, creating a punch-through-stop (PTS) in each region, causing each PTS to diffuse across a top portion of the substrate, and creating full fin(s) in each region from the partial fin(s).

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.

Abstract: A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate.

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.

Abstract: A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate.

Abstract: Embodiments herein provide device isolation in a complimentary metal-oxide fin field effect transistor. Specifically, a semiconductor device is formed with a retrograde doped layer over a substrate to minimize a source to drain punch-through leakage. A set of high mobility channel fins is formed over the retrograde doped layer, each of the set of high mobility channel fins comprising a high mobility channel material (e.g., silicon or silicon-germanium). The retrograde doped layer may be formed using an in situ doping process or a counter dopant retrograde implant. The device may further include a carbon liner positioned between the retrograde doped layer and the set of high mobility channel fins to prevent carrier spill-out to the high mobility channel fins.