Patents by Inventor Steven John Halter

Steven John Halter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • HARDWARE MANAGED POWER COLLAPSE AND CLOCK WAKE-UP FOR MEMORY MANAGEMENT UNITS AND DISTRIBUTED VIRTUAL MEMORY NETWORKS
    Publication number: 20190324512
    Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Inventors: Jason Edward PODAIMA, Christophe Denis Bernard AVOINNE, Manokanthan SOMASUNDARAM, Sina DENA, Paul Christopher John WIERCIENSKI, Bohuslav RYCHLIK, Steven John HALTER, Jaya Prakash SUBRAMANIAM GANASAN, Myil RAMKUMAR, Dipti Ranjan PAL
  • Hardware managed power collapse and clock wake-up for memory management units and distributed virtual memory networks
    Patent number: 10386904
    Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: August 20, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Jason Edward Podaima, Christophe Denis Bernard Avoinne, Manokanthan Somasundaram, Sina Dena, Paul Christopher John Wiercienski, Bohuslav Rychlik, Steven John Halter, Jaya Prakash Subramaniam Ganasan, Myil Ramkumar, Dipti Ranjan Pal
  • HARDWARE MANAGED POWER COLLAPSE AND CLOCK WAKE-UP FOR MEMORY MANAGEMENT UNITS AND DISTRIBUTED VIRTUAL MEMORY NETWORKS
    Publication number: 20170285705
    Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.
    Type: Application
    Filed: March 31, 2016
    Publication date: October 5, 2017
    Inventors: Jason Edward PODAIMA, Christophe Denis Bernard AVOINNE, Manokanthan SOMASUNDARAM, Sina DENA, Paul Christopher John WIERCIENSKI, Bohuslav RYCHLIK, Steven John HALTER, Jaya Prakash SUBRAMANIAM GANASAN, Myil RAMKUMAR, Dipt Ranjan PAL
  • Hardware enforced output security settings
    Patent number: 8910307
    Abstract: Generally, aspects of this disclosure are directed to copy protection techniques. Areas in memory may be secured to establish a secure memory area in the memory that is not accessible by unauthorized clients. A request to decode video content stored in the secure memory area may be received. If the video content to be decoded is stored in the secure memory area, a first MMU associated with the hardware decoder may enforce a rule that the video content is to be decoded into one or more output buffers in the secure memory area. A request to display the decoded video content stored in the secure memory area may be received. If the decoded video content is stored in the secure memory area, a second MMU associated with a hardware display processor may enforce a rule that a secure link be established between the hardware display processor and an output device.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: December 9, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Sudeep Ravi Kottilingal, Gary Arthur Ciambella, Steven John Halter
  • HARDWARE ENFORCED OUTPUT SECURITY SETTINGS
    Publication number: 20130305342
    Abstract: Generally, aspects of this disclosure are directed to copy protection techniques. Areas in memory may be secured to establish a secure memory area in the memory that is not accessible by unauthorized clients. A request to decode video content stored in the secure memory area may be received. If the video content to be decoded is stored in the secure memory area, a first MMU associated with the hardware decoder may enforce a rule that the video content is to be decoded into one or more output buffers in the secure memory area. A request to display the decoded video content stored in the secure memory area may be received. If the decoded video content is stored in the secure memory area, a second MMU associated with a hardware display processor may enforce a rule that a secure link be established between the hardware display processor and an output device.
    Type: Application
    Filed: December 14, 2012
    Publication date: November 14, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Sudeep Ravi Kottilingal, Gary Arthur Ciambella, Steven John Halter