Abstract: Devices, systems, and methods for applying a dielectrophoretic force on a particle include: a cell defining at least one channel for confining the particle; and a first electrode and a second electrode electrically isolated from the first electrode, at least one of the first and second electrodes being formed from a two-dimensional (2D) material providing an atomically sharp edge. The first and second electrodes are arranged sufficiently close to one another and sufficiently close to the channel such that application of a sufficient voltage across the first and second electrodes generates an electric field in at least part of the channel, the electric field having an electric field gradient sufficient to apply the dielectrophoretic force on the particle in the channel.

Abstract: A dielectrophoretic (DEP) sensor includes a graphene electrode adjacent a channel for confining a target particle in a liquid, a surface probe attached to a surface of the graphene electrode, the surface probe having a selective reaction with the target particle, and a voltage source electrically connected to the graphene electrode and configured to apply a voltage to the graphene electrode to cause DEP trapping of the target particle at the graphene electrode.

Abstract: Devices, systems, and methods for applying a dielectrophoretic force on a particle include: a cell defining at least one channel for confining the particle; and a first electrode and a second electrode electrically isolated from the first electrode, at least one of the first and second electrodes being formed from a two-dimensional (2D) material providing an atomically sharp edge. The first and second electrodes are arranged sufficiently close to one another and sufficiently close to the channel such that application of a sufficient voltage across the first and second electrodes generates an electric field in at least part of the channel, the electric field having an electric field gradient sufficient to apply the dielectrophoretic force on the particle in the channel.

Abstract: Devices, systems, and methods for applying a dielectrophoretic force on a particle include: a cell defining at least one channel for confining the particle; and a first electrode and a second electrode electrically isolated from the first electrode, at least one of the first and second electrodes being formed from a two-dimensional (2D) material providing an atomically sharp edge. The first and second electrodes are arranged sufficiently close to one another and sufficiently close to the channel such that application of a sufficient voltage across the first and second electrodes generates an electric field in at least part of the channel, the electric field having an electric field gradient sufficient to apply the dielectrophoretic force on the particle in the channel.

Abstract: Devices, systems, and methods for applying a dielectrophoretic force on a particle include: a cell defining at least one channel for confining the particle; and a first electrode and a second electrode electrically isolated from the first electrode, at least one of the first and second electrodes being formed from a two-dimensional (2D) material providing an atomically sharp edge. The first and second electrodes are arranged sufficiently close to one another and sufficiently close to the channel such that application of a sufficient voltage across the first and second electrodes generates an electric field in at least part of the channel, the electric field having an electric field gradient sufficient to apply the dielectrophoretic force on the particle in the channel.

Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

Abstract: A DRAM cell and method for storing information in a dynamic random access memory using an electrostatic actuator beam to make an electrical connection between a storage capacitor and a bit line.

Abstract: A DRAM cell and method for storing information in a dynamic random access memory using an electrostatic actuator beam to make an electrical connection between a storage capacitor and a bit line.

Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.

Abstract: A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.

Abstract: A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.

Abstract: A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.

Abstract: A layered structure for forming electronic devices thereon is provided. The layered structure includes an over-shoot layer, Si1?yGey, within a relaxed Si1?xGex layer, wherein y=X+Z and Z is in the range from 0.01 to 0.1 and X is from 0.35 to 0.5. The over-shoot layer has a thickness that is less than its critical thickness.

Abstract: An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an n- or p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.

Abstract: A structure and a method are disclosed of an enhanced T-gate for modulation doped field effect transistors (MODFETs). The enhanced T-gate has insulator spacer layers sandwiching the neck portion of the T-gate. The spacer layers are thinner than the T-bar portion overhang. The insulating layer provides mechanical support and protects the vulnerable neck portion of the T-gate from chemical attack during subsequent device processing, making the T-gate structure highly scalable and improving yield. The use of thin conformal low dielectric constant insulating layers ensures a low parasitic gate capacitance, and reduces the risk of shorting gate and source metallurgy when source-to-gate spacings are reduced to smaller dimensions.

Abstract: A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.

Abstract: A layered structure for forming electronic devices thereon is provided. The layered structure includes an over-shoot layer, Si1-yGey, within a relaxed Si1-xGex layer, wherein y=X+Z and Z is in the range from 0.01 to 0.1 and X is from 0.35 to 0.5. The over-shoot layer has a thickness that is less than its critical thickness.

Abstract: An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an n- or p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.