Patents by Inventor Steven John Koester

Steven John Koester has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180361400
    Abstract: Devices, systems, and methods for applying a dielectrophoretic force on a particle include: a cell defining at least one channel for confining the particle; and a first electrode and a second electrode electrically isolated from the first electrode, at least one of the first and second electrodes being formed from a two-dimensional (2D) material providing an atomically sharp edge. The first and second electrodes are arranged sufficiently close to one another and sufficiently close to the channel such that application of a sufficient voltage across the first and second electrodes generates an electric field in at least part of the channel, the electric field having an electric field gradient sufficient to apply the dielectrophoretic force on the particle in the channel.
    Type: Application
    Filed: June 18, 2018
    Publication date: December 20, 2018
    Inventors: Sang-Hyun Oh, Steven John Koester
  • Patent number: 8766410
    Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Josephine Chang, Leland Chang, Brian L. Ji, Steven John Koester, Amlan Majumdar
  • Patent number: 8432723
    Abstract: A DRAM cell and method for storing information in a dynamic random access memory using an electrostatic actuator beam to make an electrical connection between a storage capacitor and a bit line.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: April 30, 2013
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Leland Chang, Michael A. Guillorn, Brian J. Li, Steven John Koester
  • Publication number: 20120195102
    Abstract: A DRAM cell and method for storing information in a dynamic random access memory using an electrostatic actuator beam to make an electrical connection between a storage capacitor and a bit line.
    Type: Application
    Filed: January 28, 2011
    Publication date: August 2, 2012
    Applicant: International Business Machines Corporation
    Inventors: Josephine B. Chang, Leland Chang, Michael A. Guillorn, Brian J. Li, Steven John Koester
  • Publication number: 20110233634
    Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
    Type: Application
    Filed: June 6, 2011
    Publication date: September 29, 2011
    Applicant: International Business Machines Corporation
    Inventors: Jin Cai, Josephine Chang, Leland Chang, Brian L. Ji, Steven John Koester, Amlan Majumdar
  • Patent number: 7985633
    Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: July 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Josephine Chang, Leland Chang, Brian L. Ji, Steven John Koester, Amlan Majumdar
  • Publication number: 20090108314
    Abstract: Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
    Type: Application
    Filed: October 30, 2007
    Publication date: April 30, 2009
    Applicant: International Business Machines Corporation
    Inventors: Jin Cai, Josephine Chang, Leland Chang, Brian L. Ji, Steven John Koester, Amlan Majumdar
  • Patent number: 7504311
    Abstract: A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: March 17, 2009
    Assignee: International Business Machines Corporation
    Inventors: Steven John Koester, Devendra Kumar Sadana, Ghavam G. Shahidi
  • Patent number: 7282425
    Abstract: A method for fabricating a semiconductor substrate includes epitaxially growing an elemental semiconductor layer on a compound semiconductor substrate. An insulating layer is deposited on top of the elemental semiconductor layer, so as to form a first substrate. The first substrate is wafer bonded onto a monocrystalline Si substrate, such that the insulating layer bonds with the monocrystalline Si substrate. A semiconductor device includes a monocrystalline substrate, and a dielectric layer formed on the monocrystalline substrate. A semiconductor compound is formed on the dielectric layer and an elemental semiconductor material formed in proximity of the semiconductor compound and lattice-matched to the semiconductor compound.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: October 16, 2007
    Assignee: International Business Machines Corporation
    Inventors: Steven John Koester, Devendra Kumar Sadana, Ghavam G. Shahidi
  • Patent number: 7183175
    Abstract: A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.
    Type: Grant
    Filed: July 1, 2005
    Date of Patent: February 27, 2007
    Assignee: International Business Machines Corporation
    Inventors: Steven John Koester, Klaus Dietrich Beyer, Michael John Hargrove, Kern Rim, Kevin Kok Chan
  • Patent number: 7084431
    Abstract: A layered structure for forming electronic devices thereon is provided. The layered structure includes an over-shoot layer, Si1?yGey, within a relaxed Si1?xGex layer, wherein y=X+Z and Z is in the range from 0.01 to 0.1 and X is from 0.35 to 0.5. The over-shoot layer has a thickness that is less than its critical thickness.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: August 1, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jack Oon Chu, Richard Hammond, Khalid EzzEldin Ismail, Steven John Koester, Patricia May Mooney, John A. Ott
  • Patent number: 7083998
    Abstract: An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an n- or p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: August 1, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jack Oon Chu, Khalid EzzEldin Ismail, Steven John Koester, Bernd-Ulrich H. Klepser
  • Patent number: 6972440
    Abstract: A structure and a method are disclosed of an enhanced T-gate for modulation doped field effect transistors (MODFETs). The enhanced T-gate has insulator spacer layers sandwiching the neck portion of the T-gate. The spacer layers are thinner than the T-bar portion overhang. The insulating layer provides mechanical support and protects the vulnerable neck portion of the T-gate from chemical attack during subsequent device processing, making the T-gate structure highly scalable and improving yield. The use of thin conformal low dielectric constant insulating layers ensures a low parasitic gate capacitance, and reduces the risk of shorting gate and source metallurgy when source-to-gate spacings are reduced to smaller dimensions.
    Type: Grant
    Filed: January 2, 2004
    Date of Patent: December 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: Dinkar Singh, Katherine Lynn Saenger, Vishnubhai V. Patel, Alfred Grill, Steven John Koester
  • Patent number: 6858502
    Abstract: A method and a layered heterostructure for forming p-channel field effect transistors is described incorporating a plurality of semiconductor layers on a semiconductor substrate, a composite channel structure of a first epitaxial Ge layer and a second compressively strained SiGe layer having a higher barrier or a deeper confining quantum well and having extremely high hole mobility. The invention overcomes the problem of a limited hole mobility for a p-channel device with only a single compressively strained SiGe channel layer.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: February 22, 2005
    Assignee: International Business Machines Corporation
    Inventors: Jack Oon Chu, Richard Hammond, Khalid EzzEldin Ismail, Steven John Koester, Patricia May Mooney, John A. Ott
  • Publication number: 20040227154
    Abstract: A layered structure for forming electronic devices thereon is provided. The layered structure includes an over-shoot layer, Si1-yGey, within a relaxed Si1-xGex layer, wherein y=X+Z and Z is in the range from 0.01 to 0.1 and X is from 0.35 to 0.5. The over-shoot layer has a thickness that is less than its critical thickness.
    Type: Application
    Filed: April 26, 2004
    Publication date: November 18, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jack Oon Chu, Richard Hammond, Khalid EzzEldin Ismail, Steven John Koester, Patricia May Mooney, John A. Ott
  • Patent number: 6784466
    Abstract: An integrated optoelectronic circuit and process for making is described incorporating a photodetector and a MODFET on a chip. The chip contains a single-crystal semiconductor substrate, a buffer layer of SiGe graded in composition, a relaxed SiGe layer, a quantum well layer, an undoped SiGe spacer layer and a doped SiGe supply layer. The photodetector may be a metal-semiconductor-metal (MSM) or a p-i-n device. The detector may be integrated with an n- or p-type MODFET, or both in a CMOS configuration, and the MODFET can incorporate a Schottky or insulating gate. The invention overcomes the problem of producing Si-manufacturing-compatible monolithic high-speed optoelectronic circuits for 850 nm operation by using epixially-grown Si/SiGe heterostructure layers.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: August 31, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jack Oon Chu, Khalid EzzEldin Ismail, Steven John Koester, Bernd-Ulrich H. Klepser
  • Publication number: 20040164373
    Abstract: A structure, and a method for fabricating the structure, for the isolation of electronic devices is disclosed. The electronic devices are processed in substrates comprising a SiGe based layer underneath a strained Si layer. The isolation structure comprises a trench extending downward from the substrate top surface and penetrating into the SiGe based layer, forming a sidewall in the substrate. An epitaxial Si liner is selectively deposited onto the trench sidewall, and subsequently thermally oxidized. The trench is filled with a trench dielectric, which protrudes above the substrate top surface.
    Type: Application
    Filed: February 25, 2003
    Publication date: August 26, 2004
    Inventors: Steven John Koester, Klaus Dietrich Beyer, Michael John Hargrove, Kern Rim, Kevin Kok Chan
  • Publication number: 20040140506
    Abstract: A structure and a method are disclosed of an enhanced T-gate for modulation doped field effect transistors (MODFETs). The enhanced T-gate has insulator spacer layers sandwiching the neck portion of the T-gate. The spacer layers are thinner than the T-bar portion overhang. The insulating layer provides mechanical support and protects the vulnerable neck portion of the T-gate from chemical attack during subsequent device processing, making the T-gate structure highly scalable and improving yield. The use of thin conformal low dielectric constant insulating layers ensures a low parasitic gate capacitance, and reduces the risk of shorting gate and source metallurgy when source-to-gate spacings are reduced to smaller dimensions.
    Type: Application
    Filed: January 2, 2004
    Publication date: July 22, 2004
    Applicant: International Business Machines Corporation
    Inventors: Dinkar Singh, Katherine Lynn Saenger, Vishnubhai V. Patel, Alfred Grill, Steven John Koester
  • Patent number: 6740535
    Abstract: A structure and a method are disclosed of an enhanced T-gate for modulation doped field effect transistors (MODFETs). The enhanced T-gate has insulator spacer layers sandwiching the neck portion of the T-gate. The spacer layers are thinner than the T-bar portion overhang. The insulating layer provides mechanical support and protects the vulnerable neck portion of the T-gate from chemical attack during subsequent device processing, making the T-gate structure highly scalable and improving yield. The use of thin conformal low dielectric constant insulating layers ensures a low parasitic gate capacitance, and reduces the risk of shorting gate and source metallurgy when source-to-gate spacings are reduced to smaller dimensions.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: May 25, 2004
    Assignee: International Business Machines Corporation
    Inventors: Dinkar Singh, Katherine Lynn Saenger, Vishnubhai V. Patel, Alfred Grill, Steven John Koester
  • Publication number: 20040016972
    Abstract: A structure and a method are disclosed of an enhanced T-gate for modulation doped field effect transistors (MODFETs). The enhanced T-gate has insulator spacer layers sandwiching the neck portion of the T-gate. The spacer layers are thinner than the T-bar portion overhang. The insulating layer provides mechanical support and protects the vulnerable neck portion of the T-gate from chemical attack during subsequent device processing, making the T-gate structure highly scalable and improving yield. The use of thin conformal low dielectric constant insulating layers ensures a low parasitic gate capacitance, and reduces the risk of shorting gate and source metallurgy when source-to-gate spacings are reduced to smaller dimensions.
    Type: Application
    Filed: July 29, 2002
    Publication date: January 29, 2004
    Inventors: Dinkar Singh, Katherine Lynn Saenger, Vishnubhai V. Patel, Alfred Grill, Steven John Koester