Abstract: A computer system (10) implements a memory allocator that employs a data structure (FIG. 3) to maintain an inventory of dynamically allocated memory available to receive new data. It receives from one or more programs requests that it allocate memory from a dynamically allocable memory “heap.” It responds to such requests by performing the requested allocation and removing the thus-allocated memory block from the inventory. Conversely, it adds to the inventory memory blocks that the supported program or programs request be freed. In the process, it monitors the frequencies with which memory blocks of various sizes are allocated, and it projects from those frequencies future-demand values for memory blocks of those sizes. It then splits larger blocks into smaller ones preemptively, i.e., before a request for the result of the splitting.

Abstract: A computer system (10) implements a memory allocator that employs a data structure (FIG. 3) to maintain an inventory of dynamically allocated memory available to receive new data. It receives from one or more programs requests that it allocate memory from a dynamically allocable memory “heap.” It responds to such requests by performing the requested allocation and removing the thus-allocated memory block from the inventory. Conversely, it adds to the inventory memory blocks that the supported program or programs request be freed. In the process, it monitors the frequencies with which memory blocks of various sizes are allocated, and it projects from those frequencies future-demand values for memory blocks of those sizes. It then splits larger blocks into smaller ones preemptively, i.e., before a request for the result of the splitting.

Abstract: A computer system (10) implements a memory allocator that employs a data structure (FIG. 3) to maintain an inventory of dynamically allocated memory available to receive new data. It receives from one or more programs requests that it allocate memory from a dynamically allocable memory “heap.” It responds to such requests by performing the requested allocation and removing the thus-allocated memory block from the inventory. Conversely, it adds to the inventory memory blocks that the supported program or programs request be freed. In the process, it monitors the frequencies with which memory blocks of various sizes are allocated, and it projects from those frequencies future demand for memory blocks of those sizes. To split a relatively large block in order to meet an actual or expected request for a smaller block, it bases its selection of the larger block to be split on whether the supply of free blocks of the larger block's size is great enough to meet the expected demand for such blocks.

Abstract: A computer system (10) implements a memory allocator that employs a data structure (FIG. 3) to maintain an inventory of dynamically allocated memory available to receive new data. It receives from one or more programs requests that it allocate memory from a dynamically allocable memory “heap.” It responds to such requests by performing the requested allocation and removing the thus-allocated memory block from the inventory. Conversely, it adds to the inventory memory blocks that the supported program or programs request be freed. In the process, it monitors the frequencies with which memory blocks of different sizes are allocated, and it projects from those frequencies future demand for different-sized memory blocks. When it needs to coalesce multiple smaller blocks to fulfil an actual or expected request for a larger block, it bases its selection of which constituent blocks to coalesce on whether enough free blocks of a constituent block's size exist to meet the projected demand for them.

Abstract: A garbage collector employs a plurality of task queues for a parallel-execution operation in a garbage-collection cycle. Each task queue is associated with a different ordered pair of the threads that perform the parallel-execution operation in parallel. One of the threads, referred to as that task queue's “enqueuer” thread, is the only one that can “push” onto that queue an identifier of a dynamically identified task. The other thread, referred to as that task queue's “dequeuer,” is the only one that can “pop” tasks from that task queue for execution. Since, for each task queue, there is only one thread that can “push” task identifiers on to it and only one thread that can “pop” task identifiers from it, the garbage collector can share dynamically identified tasks optimally among its threads without suffering the cost imposed by making combinations of otherwise separate machine instructions atomic.

Abstract: In response to source code that represents instructions for dynamically allocating memory to objects, a compiler/interpreter produces instructions that implement a garbage collector. The garbage collector operates in garbage-collection cycles, which include parallel-execution operations such as locating reachable objects. Each thread maintains a respective task queue onto which it pushes identifiers of objects thus found and from which it pops those identifiers in order to begin the tasks of locating the further objects to which objects specified by the thus-popped identifiers refer. A thread's access to its respective task queue ordinarily occurs on a last-in, first-out basis, but the access mode switches to a first-in, first-out basis if the number of task-queue entries exceeds a predetermined threshold.

Abstract: Interconnection subsystems having diverse topologies, for interconnecting small numbers of nodes having a predetermined maximum degree in a multiprocessor computer system, include subsystems broadly classified into a number of general classes based on their topologies, including a "polygonal" class, a "ladder" class and a "tiled" class. In topologies of the polygonal class, a majority of the nodes in the multiprocessor computer system are connected in a ring and the remaining nodes are connected to the nodes in the ring, and in some cases also to each other. In topologies of the ladder class, the nodes are interconnected in a "ladder" topology comprising a series of nodes connected in a ring, the ring corresponding to one standard of a ladder topology folded on itself. Each node in the ring is connected to another node in a second series, effectively forming rungs of the ladder topology.

Abstract: Interconnection subsystems having diverse topologies, for interconnecting small numbers of nodes having a predetermined maximum degree in a multiprocessor computer system, include subsystems broadly classified into a number of general classes based on their topologies, including a "polygonal" class, a "ladder" class and a "tiled" class. In topologies of the polygonal class, a majority of the nodes in the multiprocessor computer system are connected in a ring and the remaining nodes are connected to the nodes in the ring, and in some cases also to each other. In topologies of the ladder class, the nodes are interconnected in a "ladder" topology comprising a series of nodes connected in a ring, the ring corresponding to one standard of a ladder topology folded on itself. Each node in the ring is connected to another node in a second series, effectively forming rungs of the ladder topology.

Abstract: A system and method for generating a program to enable reassignment of data items among processors in a massively-parallel computer to effect a predetermined rearrangement of address bits. The computer has a plurality of processing elements, each including a memory. Each memory includes a plurality of storage locations for storing a data item, each storage location within the computer being identified by an address, comprising a plurality of address bits having a global portion comprising a processing element identification portion and a local portion identifying the storage location within the memory of the particular processing element. The system generates a program to facilitate use of a predetermined set of tools to effect a reassignment of data items among processing elements and storage location to, in turn, effect a predetermined rearrangement of address bits. The system includes a global processing portion and a local processing portion.

Abstract: In brief summary, the invention provides a new message packet transfer system, which may be used in, for example, a multiprocessor computer system. The message packet transfer system comprises a plurality of switching nodes interconnected by communication links to define at least one cyclical packet transfer path having a predetermined diameter. The switching nodes may be connected to, for example, digital data processors and memory to form processing nodes in an multiprocessor computer system, and/or to other sources and destinations for digital data contained in the message packets. The switching nodes transfer message packets each from a respective one of the switching nodes as a respective source switching node to a respective one of the switching nodes as a respective destination switching node.

Abstract: Interconnection subsystems having diverse topologies are disclosed for interconnecting small numbers of nodes having a predetermined maximum degree in a multiprocessor computer system. The interconnection subsystems are generally classified into three diverse classes of topologies, including a "polygonal" class, a "ladder" class and a "tiled" class. In topologies of the polygonal class, a majority of the nodes in the multiprocessor computer system are connected in a ring and the remaining nodes are connected to the nodes in the ring, and in some cases also to each other. In topologies of the ladder class, the nodes are interconnected in a "ladder" topology comprising a series of nodes connected in a ring, the ring corresponding to one standard of a ladder topology folded on itself. Each node in the ring is connected to another node in a second series, effectively forming rungs of the ladder topology.

Abstract: A computer system comprises a plurality of processing elements interconnected by a communications network. The communications network has a series of network addresses each identifying a location in the network, each processing element has an associated network address in the series. The communications network transfers messages transmitted by the processing elements in accordance with a respective address portion associated with each message, thereby to transfer the messages among the processing elements. Each processing element includes a message generator and a message transmitter. The message generator generates, during a message transfer operation, a series of messages for transmission over the communications network to others of the processing elements in the system, each message having an address portion whose contents enable the communications network to transfer the message from the processing element generating the message to a processing element to receive the message.

Abstract: A massively parallel computer system including a plurality of processing nodes under control of a system controller. The processing nodes are interconnected by a plurality of communications links. Each processing node comprises at least one processor, a memory, and a router node connected to the communications links for transferring in a series of message transfer cycles messages over the communications links. The controller enables each processing node to establish a message queue in its memory. The controller further enables storage of messages received by the processing nodes for their respective processors during a message transfer cycle to be stored in the message queue.