Patents by Inventor Steven K. Jenkins
Steven K. Jenkins has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9436388Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: GrantFiled: April 7, 2016Date of Patent: September 6, 2016Assignee: International Business Machines CorporationInventors: Steven K. Jenkins, Robert B. Likovich, Jr., Michael R. Trombley
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Publication number: 20160216897Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: ApplicationFiled: April 7, 2016Publication date: July 28, 2016Inventors: STEVEN K. JENKINS, ROBERT B. LIKOVICH, JR., MICHAEL R. TROMBLEY
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Patent number: 9343123Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: GrantFiled: September 10, 2014Date of Patent: May 17, 2016Assignee: International Business Machines CorporationInventors: Steven K. Jenkins, Robert B. Likovich, Jr., Michael R. Trombley
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Publication number: 20140379979Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: ApplicationFiled: September 10, 2014Publication date: December 25, 2014Inventors: STEVEN K. JENKINS, ROBERT B. LIKOVICH, JR., MICHAEL R. TROMBLEY
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Patent number: 8902683Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: GrantFiled: August 27, 2013Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Steven K. Jenkins, Robert B. Likovich, Jr., Michael R. Trombley
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Publication number: 20130346686Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: ApplicationFiled: August 27, 2013Publication date: December 26, 2013Applicant: International Business Machines CorporationInventors: STEVEN K. JENKINS, ROBERT B. LIKOVICH, JR., MICHAEL R. TROMBLEY
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Patent number: 8547760Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: GrantFiled: June 29, 2011Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Steven K. Jenkins, Robert B. Likovich, Jr., Michael R. Trombley
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Publication number: 20130003475Abstract: Memory access alignment in a double data rate (‘DDR’) system, including: executing, by a memory controller, one or more write operations to a predetermined address of a DDR memory module, including sending to the DDR memory module a predetermined amount of data of a predetermined pattern along with a data strobe signal; executing, by the memory controller, a plurality of read operations from the predetermined address of the DDR memory module, including capturing data transmitted from the DDR memory module; and determining, by the memory controller, a read adjust value and a write adjust value in dependence upon the data captured in response to the read operations.Type: ApplicationFiled: June 29, 2011Publication date: January 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Steven K. Jenkins, Robert B. Likovich, JR., Michael R. Trombley
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Patent number: 8140803Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a processor memory system, which may include a processor and a memory controller in communication with the processor through a bus. The memory controller may include a delay circuit to receive an early read indicator corresponding to read data from a memory, the delay circuit to delay the early read indicator in accordance with a pre-determined delay such that the early read indicator is passed to the bus in advance of the read data, and a delay adjustment circuit to dynamically adjust the pre-determined delay associated with the delay circuit responsive to a change in operational speed of the processor or the bus.Type: GrantFiled: May 4, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: James J. Allen, Jr., Steven K. Jenkins, James A. Mossman, Michael R. Trombley
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Patent number: 8032713Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a storage device, circuitry for providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to the storage device that can be speculatively issued, and circuitry for intermixing demand accesses and speculative accesses in accordance with the speculative access threshold.Type: GrantFiled: May 5, 2008Date of Patent: October 4, 2011Assignee: International Business Machines CorporationInventors: James J. Allen, Jr., Steven K. Jenkins, James A. Mossman, Michael R. Trombley
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Patent number: 8028257Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system is provided. A scheduling algorithm pre-computes return time data for data connected to DRAM buffer chips and stores the return time data in a table. The return time data is expressed as data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.Type: GrantFiled: April 28, 2008Date of Patent: September 27, 2011Assignee: International Business Machines CorporationInventors: James J. Allen, Jr., Steven K. Jenkins, Michael R. Trombley
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Patent number: 7937533Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold.Type: GrantFiled: May 4, 2008Date of Patent: May 3, 2011Assignee: International Business Machines CorporationInventors: James J. Allen, Jr., Steven K. Jenkins, James A. Mossman, Michael R. Trombley
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Patent number: 7660952Abstract: A method and system for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system. A scheduling algorithm pre-computes return time data for data connected to all DRAM buffer chips and stores the return time data in a table. The return time data is expressed as a set of data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector representing a compilation of data return time vectors of all executing requests to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.Type: GrantFiled: March 1, 2007Date of Patent: February 9, 2010Assignee: International Business Machines CorporationInventors: James J. Allen, Jr., Steven K. Jenkins, Michael R. Trombley
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Patent number: 7660951Abstract: Efficient transfer of data to and from random access memory is described. Multiple request sources and a memory system comprise memory modules having memory banks, each bank containing rows of data. The retrieval comprises transferring all data pursuant to a given request by one source before any data is transferred pursuant to a subsequent request from said second source. This retrieval is achieved using a memory arbiter that implements an algorithm for atomic read/write. Each bank is assigned a FIFO buffer by the arbiter to store access requests. The access requests are arbitrated, and an encoded value of a winner of arbitration is loaded into the relevant FIFO buffer(s) before choosing the next winner. When an encoded value reaches the head of the buffer, all associated data is accessed in the given bank before accessing data for another request source.Type: GrantFiled: February 26, 2008Date of Patent: February 9, 2010Assignee: Inernational Business Machines CorporationInventors: Steven K. Jenkins, Laura A. Weaver
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Patent number: 7657771Abstract: Methods and system for reducing latency associated with a read operation in a processor memory system are provided. In one implementation, the method includes receiving an early indicator corresponding to read data from a memory, delaying the early indicator in accordance with a pre-determined delay such that the early read indicator is passed to a bus in advance of the read data; and dynamically adjusting the pre-determined delay using an adjustment delay circuit, the pre-determined delay being adjusted responsive to a change in operational speed of the bus or change in operational speed of a processor coupled to the bus.Type: GrantFiled: January 9, 2007Date of Patent: February 2, 2010Assignee: International Business Machines CorporationInventors: James J. Allen, Jr., Steven K. Jenkins, James A. Mossman, Michael R. Trombley
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Publication number: 20090150618Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a storage device, circuitry for providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to the storage device that can be speculatively issued, and circuitry for intermixing demand accesses and speculative accesses in accordance with the speculative access threshold.Type: ApplicationFiled: May 5, 2008Publication date: June 11, 2009Inventors: James J. Allen, JR., Steven K. Jenkins, James A. Mossman, Michael R. Trombley
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Publication number: 20090150572Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold.Type: ApplicationFiled: May 4, 2008Publication date: June 11, 2009Inventors: JAMES J. ALLEN, JR., Steven K. Jenkins, James A. Mossman, Michael R. Trombley
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Publication number: 20080215832Abstract: A method and system for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system. A scheduling algorithm pre-computes return time data for data connected to all DRAM buffer chips and stores the return time data in a table. The return time data is expressed as a set of data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector representing a compilation of data return time vectors of all executing requests to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.Type: ApplicationFiled: March 1, 2007Publication date: September 4, 2008Inventors: James J. Allen, Steven K. Jenkins, Michael R. Trombley
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Publication number: 20080215783Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system is provided. A scheduling algorithm pre-computes return time data for data connected to DRAM buffer chips and stores the return time data in a table. The return time data is expressed as data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.Type: ApplicationFiled: April 28, 2008Publication date: September 4, 2008Inventors: James J. Allen, Steven K. Jenkins, Michael R. Trombley
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Publication number: 20080209095Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a processor memory system, which may include a processor and a memory controller in communication with the processor through a bus. The memory controller may include a delay circuit to receive an early read indicator corresponding to read data from a memory, the delay circuit to delay the early read indicator in accordance with a pre-determined delay such that the early read indicator is passed to the bus in advance of the read data, and a delay adjustment circuit to dynamically adjust the pre-determined delay associated with the delay circuit responsive to a change in operational speed of the processor or the bus.Type: ApplicationFiled: May 4, 2008Publication date: August 28, 2008Inventors: JAMES J. ALLEN, Steven K. Jenkins, James A. Mossman, Michael R. Trombley