Abstract: A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.

Abstract: A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.

Abstract: A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.

Abstract: A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.

Abstract: A representative reconfigurable processing circuit and a reconfigurable arithmetic circuit are disclosed, each of which may include input reordering queues; a multiplier shifter and combiner network coupled to the input reordering queues; an accumulator circuit; and a control logic circuit, along with a processor and various interconnection networks. A representative reconfigurable arithmetic circuit has a plurality of operating modes, such as floating point and integer arithmetic modes, logical manipulation modes, Boolean logic, shift, rotate, conditional operations, and format conversion, and is configurable for a wide variety of multiplication modes. Dedicated routing connecting multiplier adder trees allows multiple reconfigurable arithmetic circuits to be reconfigurably combined, in pair or quad configurations, for larger adders, complex multiplies and general sum of products use, for example.

Abstract: Methods of authenticating a combination of a programmable IC and a non-volatile memory device, where the non-volatile memory device stores a configuration data stream implementing a user design in the programmable IC. A first identifier unique to the programmable IC is stored in non-volatile memory in the programmable IC. A second identifier unique to the non-volatile memory device is stored in the non-volatile memory device. As part of the process in which the configuration data stream is used to program the programmable IC with the user design, a function is performed on the two identifiers, producing a key specific to the programmable IC/non-volatile memory device combination. The key is then compared to an expected value. When the key matches the expected value, the user design is enabled. When the key does not match the expected value, at least a portion of the user design is disabled.

Abstract: Methods of authenticating a user design in a programmable integrated circuit. The methods utilize an identifier unique to the programmable IC and a data word taken from the user design. The data word can be unique to the design and can include a string of data taken from the configuration data for the design, or the values of circuit nodes read from selected points throughout the design. A function is performed on the identifier and the data word, producing a key specific to the user design as implemented in that programmable IC. The key is compared to an expected value. When the key matches the expected value, the user design is enabled. When the key does not match the expected value, at least a portion of the user design is disabled. Circuitry for performing the steps of the method can be implemented in the programmable resources of the programmable IC.

Abstract: A system for authentication of information provided to an integrated circuit, a method for rights management of an integrated circuit, and a method for configuring a programmable logic device are described. A memory is coupled to a programmable logic device. The memory includes an array of memory cells and storage devices. The storage devices provide a first storage space and a second storage space. The first storage space is for storing a first identifier. The second storage space is for storing a second identifier, which is a transformation of the first identifier. The array of memory cells is for storing configuration information to configure programmable logic of the programmable logic device. The configuration information includes authentication logic information.

Abstract: A system for authentication of information provided to an integrated circuit, a method for rights management of an integrated circuit, and a method for configuring a programmable logic device are described. A memory is coupled to a programmable logic device. The memory includes an array of memory cells and storage devices. The storage devices provide a first storage space and a second storage space. The first storage space is for storing a first identifier. The second storage space is for storing a second identifier, which is a transformation of the first identifier. The array of memory cells is for storing configuration information to configure programmable logic of the programmable logic device. The configuration information includes authentication logic information.

Abstract: A method is provided to program a memory device through a JTAG interface of an attached component with programmable logic, wherein the memory device does not have a JTAG interface. Initially, programming hardware to provide for programming of the attached memory is downloaded into the component via the component's JTAG interface. The programmed component then becomes a serial data link between the JTAG port attached to a host programmer and a non-JTAG port attached to the memory device. The circuitry downloaded or programmed into the component controls the timing and the protocol to program the external memory.

Abstract: An interface between a programmable device and an external device coupled to the programmable device is described. The interface includes configurable control pins for providing control signals to the external device. The programmable device may be a field programmable gate array and the external device may be a nonvolatile memory. In some cases, the interface may be used to provide a byte-wide, or other parallel, interface. After configuration, the pins of the interface may be reclaimed and used for other purposes, such as accessing one or more external memories or other devices connected to a bus.

Abstract: A method and structure for configuring a programmable logic device (PLD) from a serial peripheral interface (SPI) based serial memory. The type of the SPI memory is initially identified by the PLD. The PLD then selects the appropriate read command in response to the SPI memory type. The PLD then issues the read command to the SPI memory. In response, the SPI memory continuously provides a set of configuration data to the PLD. The PLD is configured in response to the configuration data. The PLD can identify the SPI memory type in response to control signals on pins of the PLD. Alternately, the PLD can identify the SPI memory type by performing a search. The search can include issuing a plurality of known read commands to the SPI memory, and then determining which read command causes the SPI memory to respond.

Abstract: A system and method are described for securing a configurable system on a chip (CSoC) or other programmable chip design to prevent unauthorized copying. A processor reads instructions from a memory device. The processor reads an identification code from an identification code provider. If no identification code has been previously imprinted on the memory, the processor imprints the provider identification code into the memory. If an identification code is already present, the memory identification code is compared with the provider identification code. If the memory identification code matches with the provider identification code, the processor is allowed to perform the program present on the memory. If the memory identification code does not match with the provider identification code, appropriate security countermeasures are taken. The program and identification code can be further encrypted on the memory for greater security, using the provider identification code as the encryption key.

Abstract: An integrated circuit includes a debugging unit which uses a multi-master general purpose bus within the IC to perform debugging functions. The storage elements of the IC are mapped into the address space of the general purpose bus. The debugging unit can operate as a bus master and read from or write to the storage elements of the integrated circuit directly with the general purpose bus. Thus, the integrated circuit can be rapidly configured for testing and debugging. Furthermore, the debugging unit can work with a breakpoint unit on the IC to detect and analyze specific situations on the IC.

Abstract: The more highly integrated programmable circuits include several kinds of resources for implementing the user's logic diagram. The resources provided in the chip hardware are intended to implement functions commonly specified by a user, in order for a complex chip to efficiently implement a complex design, the features called for in the design must be matched with the resources offered in the chip hardware. The present invention evaluates a user's logic diagram in comparison to resources available on a particular chip and matches a plurality of features in the design to resources in the chip which can efficiently implement those features.

Abstract: A method of state splitting in a state machine includes determining a number N of logic levels, i.e. CLB levels, for each state in a state machine. Number N is equal to N.sub.i-1 +log.sub.k f.sub.i wherein "k" is the number of input lines to a CLB, "i" is a particular node in a particular hierarchial level in the Boolean logic, and "f" is the number of fanin transitions to the particular node. An average number N(AV) as well as a maximum number N(MAX) of CLBs to implement the states in the state machine are also determined. Then, predetermined exit criteria are checked. One exit criterion includes determining that the maximum number N(MAX) is not associated with a state register, but is instead associated with an output, for example. Another exit criterion includes providing a ratio by dividing the maximum number N(MAX) by the average number N(AV). If the ratio is less than or equal to a split-factor, then this exit criterion is met. In one embodiment, the split factor is between 1.5 and 2.0.

Abstract: A method is described for configuring a general symbol to represent a specific symbol indicated by a user. The specific symbols are part of a library. A general symbol for which optimized implementations have been determined and stored is configured to implement the specific function specified by a user. Implementations provided for the general symbol include special functions which provide both high speed and small chip area.

Abstract: The more highly integrated programmable circuits include several kinds of resources for implementing the user's logic diagram. The resources provided in the chip hardware are intended to implement functions commonly specified by a user. In order for a complex chip to efficiently implement a complex design, the features called for in the design must be matched with the resources offered in the chip hardware. The present invention evaluates a user's logic diagram in comparison to resources available on a particular chip and matches a plurality of features in the design to resources in the chip which can efficiently implement those features.

Abstract: A set of module generators produce optimized implementations of particular circuit logic arithmetic functions for Field Programmable Gate Arrays (FPGAs) or other digital circuits. The module generators allow a circuit designer to spend more time actually designing and less time determining device-specific implementation details. The module generators accept a high level block diagram schematic of the circuit and automatically perform the detailed circuit design, including propagation of data types (precision and type) through the circuit, and low level circuit design optimization using a library of arithmetic and logic functions. The module generators are particularly useful for designs using field programmable gate arrays because of their unique architectures and ability to implement complex functions.

Abstract: A computer aided design system for electronic digital circuitry allows the circuit designer to design a circuit using high level block components, The designer specifies data type and precision (bus width) parameters as desired for whichever circuit blocks and/or busses he desires, Then the system propagates the data types and precision throughout the design automatically to achieve circuit-wide consistency, The system can also be used to verify a circuit design for data type and bus width consistency, The system can also be used to determine the mode of operation for the circuit blocks in the circuit.