Abstract: The present disclosure concerns a method and apparatus for mapping each of a plurality of logical addresses to a physical address identifying a location in a memory device. The memory device has a plurality of columns and rows, wherein each row has a plurality of data paragraphs including data and at least one parity paragraph including parity data. Each paragraph is comprised of a plurality of contiguous columns. A physical address identifies a location of a paragraph in the memory device. To map the logical addresses to physical addresses, a determination must be made as to whether the row and column portions of each logical address identify a physical address location including parity data. If a logical address identifies a physical address location in the memory device including parity data, then the logical address is incremented until the row and column portions of the logical address identify a physical address location not including parity data.