Abstract: A hard disk simulator that comprises a timing generator controller coupled to receive address, data and control signals; a timing generator for providing a pulse in response to signals received from the timing generator controller; and an address generator coupled to receive the control or index pulse and a programmable frequency clock to generate addresses for a hard disk simulator. The address generator includes an offset counter that generates values in response to the programmable frequency clock and the control pulse. The address generator also receives a base address that corresponds to a hard disk track. The offset counter values and the base address are combined to provide an address. The present invention also includes a method of simulating a hard disk including the step of adding an offset value to a base value to simulate rotational latency of the hard disk.

Abstract: An I/O circuit including first and second I/O pads, a fuse connected between the first pad and a RAM write enable line, and a diode-connected transistor connected between the RAM write enable line and second pad. Data is written to the RAM by applying a voltage potential to the pads after which the fuse is blown by increasing the potential difference. Other forms of the invention include a resistor connected between the RAM write enable line and ground, and I/O lines connected between the pads, respectively, and a logic circuit.

Abstract: An I/O circuit including first and second I/O pads, a fuse connected between the first pad and a RAM write enable line, and a diode-connected transistor connected between the RAM write enable line and second pad. Data is written to the RAM by applying a voltage potential to the pads after which the fuse is blown by increasing the potential difference. Other forms of the invention include a resistor connected between the RAM write enable line and ground, and I/O lines connected between the pads, respectively, and a logic circuit.