Abstract: Reduction of input capacitance in an analog storage array is achieved by reducing the parasitic capacitance presented to an analog signal line. Each column of the analog storage array is coupled to the analog signal line by a separate coupling switch. The switches are activated so that no more than two columns are coupled to the analog signal line at any time, with the next column to be accessed being coupled to the analog signal line prior to access to that column, and the last column being decoupled from the analog signal line after the last cell in the column has been accessed. Further the analog signal line may provide two input ports so that alternate columns of the array are coupled to one port, and the other alternate columns are coupled to the other port so that two adjacent columns are coupled to separate ones of the two ports.

Abstract: A CMOS-compatible peak detection circuit includes a differential amplifier stage (10), an active peak holding circuit (12), and a passive peak holding circuit (14). The differential amplifier stage (10) produces an amplifier output signal that is responsive to the difference between an input signal being monitored and feedback from the active peak holding circuit (12). Both the active peak holding circuit (12) and the passive peak holding circuit (14) store a charge representing a voltage level that is indicative of the peak amplitude of the amplifier output signal during a time interval, the time interval occurring while a disable signal is inactive. The active peak holding circuit (12) provides the maximum value signal as feedback to the differential amplifier stage (10). The passive peak holding circuit (14) provides a max signal output corresponding to the maximum value to a voltage follower stage (16) that makes it available as an output when a readback enable signal goes active.

Abstract: An analog acquisition system includes an array of analog capture cells for capturing and storing a signal on an analog bus. Each capture cell in the array may be sequentially selected for sampling the signal at successive sample times. Timing for selecting a row of the analog memory array is provided by a slow shift register and timing for selecting a capture cell within the row of the analog memory array is provided by a fast tapped delay line. Additional circuitry is provided for controlling the delay of the tapped delay line such that total delay is equal to the time the slow shift register takes to transfer from one row to the next.

Abstract: A circuit breaker has two thin flat terminals embedded in an electrically insulating housing exposing respective broad flat sides of the terminals in spaced side-by-side relation to each other in a housing chamber. The circuit breaker has a thermostat metal member secured at one end to one exposed side of one terminal to mount the member extending along a chamber wall and has a contact at its opposite end to engage and disengage the other terminal to close and open a circuit in response to a selected current in the circuit. The contact comprises a material which erodes during repeated cycling of the circuit breaker. The thermostat metal member has a portion of reduced cross-sectional area adapted to burn out and separate the member into two sections to open the circuit if the contact welds or sticks to the other terminal. A stop on the housing intercepts movement of one of the member sections after burn out to avoid shorting of the circuit.

Abstract: In accordance with the present invention, a heater is included on an integrated circuit, together with a circuit for controlling the heater to selectively heat the integrated circuit and control the propagation delay time of signals passing through the integrated circuit. In a specific form of the invention, the propagation delay time of signals passing through at least a portion of an integrated circuit is measured and compared with a reference propagation delay time. The heater is controlled to increase the heat it produces when the measured propagation delay time is less than the reference propagation delay time. In addition, the heater is controlled to decrease the heat it provides when the measured propagation delay time is greater than the reference propagation delay time.

Abstract: A calibrated automatic test system includes a test station for generating digital test function codes and a test head containing a plurality of I/O pins for connection to a device under test. Each I/O pin includes a pin electronics circuit responsive to the digital test function codes for providing test signals to the device under test. The pin electronics circuits are inexpensive CMOS IC's and lack the accuracy needed to test VLSI devices at the frequencies of interest. An external calibration unit is connected to each I/O pin and data measurements are taken which represent the performance of the CMOS IC's. The data measurements are converted to calibrated function codes representing desired data values which are then stored in correction memory circuits which respond to nominal digital test function codes and substitute in their places calibrated function codes which are then supplied to the pin electronics circuits.

Abstract: An active load network for a device under test includes a logic circuit for anticipating the output state of the device under test and for turning on either a current source of a current sink to properly load its output. The current sink and current source each comprise a pair of CMOS transistors connected in series. One of each transistor pair turns on to either source or sink current and the other provides a variable impedance controlled by the voltage at its gate to regulate the amount of current. A pull-to-center transmission gate is also provided which pulls the output of the device under test to a level between a logic high and logic low when it is turned off.

Abstract: A variable impedance driver network comprises a plurality of transmission gates connected in parallel between a voltage source and an output. Each transmission gate has a predetermined nominal impedance and by turning on selective gates the overall impedance of the network may be adjusted to match that required at the output.