Patents by Inventor Steven Klein

Steven Klein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12127363
    Abstract: Embodiments disclosed herein include sockets and electronic packages with socket architectures. In an embodiment, a socket comprises a housing with a first surface and a second surface. In an embodiment, a plurality of interconnect pins pass through the housing. In an embodiment, an alignment hole is provided through the housing. In an embodiment, an alignment post extending out from the first surface of the housing is also provided.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: October 22, 2024
    Assignee: Intel Corporation
    Inventors: Feifei Cheng, Thomas Boyd, Kuang Liu, Steven A. Klein, Daniel Neumann, Mohanraj Prabhugoud
  • Publication number: 20240338425
    Abstract: In some embodiments, the present disclosure provides an exemplary method that may include steps of identifying a plurality of entities seeking to interact with each other; determining a set of artifacts associated with each entity of the plurality of entities; Utilizing a cloud-based functionality to dynamically connect at least two entities based on a determination of the set of artifacts shared between the at least two entities; dynamically integrating a plurality of protocols into an interaction session associated with the at least two entities; verifying the plurality of protocols associated with the interaction session; initiating the interaction session between at least two entities based on the plurality of protocols and the set of artifacts; and automatically modifying the interaction session to orchestrate a transfer of at least one artifact of the set of artifacts between the at least two entities.
    Type: Application
    Filed: April 4, 2024
    Publication date: October 10, 2024
    Inventors: Sangeeth Rao, Ramchand Swarna, Terry Ashby, Randall Stafford, RajSekhar Reddygari, Krishna Hegde, Jeffery Price, Lee Kenyon, Nehal Patel, Mark Stanton, Joe Rottenberg, Vijay Bandaru, Jeffrey Klein, Mitchell Herman, Otto Heilmann, Julie Hodum, Michael Ward, Michael Speed, Tim Profitt, Angelo Riccio, Steven Pirella, Pat Scaglione, Michael Stallmeyer
  • Patent number: 12097258
    Abstract: A Dectin-2 ligand vaccine adjuvant and a method of making and using the Dectin-2 ligand vaccine adjuvant in a vaccine to immunize a patient are disclosed. Also discloses is a vaccine composition comprising a Bl-Eng2 antigen and methods of using the vaccine composition to immunize a subject against a fungal infection.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: September 24, 2024
    Assignee: WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Bruce Steven Klein, Huafeng Wang, Marcel Wuethrich, Tristan Theodore Brandhorst
  • Publication number: 20240297119
    Abstract: An electronic device (100, 800, 1000) and associated methods are disclosed. In one example, the electronic device (100, 800, 1000) includes an interconnect socket (102, 302, 402, 802, 1004, 1320, 1402, 1506) that includes a liquid metal. In selected examples, the interconnect socket (102, 302, 402) includes a resilient material spacer (130, 230, 330, 430) located between pins (110, 210, 310, 410) in an array of pins (110, 210, 310, 410). In selected examples, the electronic device (1000) includes configurations to aid in de-socketing.
    Type: Application
    Filed: December 22, 2021
    Publication date: September 5, 2024
    Inventors: Srikant Nekkanty, Karumbu Meyyappan, Andres Ramirez Macias, Zhe Chen, Jeffory L. Smalley, Zhichao Zhang, Steven A. Klein, Eric Erike
  • Patent number: 12067572
    Abstract: A method for detecting and tracking tainted cryptographic wallets. The method measures a wallet's propensity to engage in criminal or suspicious activity. Naturally, transacting with a criminal is tantamount either to funding crime or laundering its proceeds, so it is in our collective interest to identify—and then monitor or quarantine—any wallet with criminal association. The method also automatically flags risky withdrawal requests in real-time for further review before committing them to the blockchain. In some embodiments, the exchange can quarantine wallets at a certain Walletscore.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: August 20, 2024
    Assignee: DMG BLOCKCHAIN SOLUTIONS, INC.
    Inventors: Timothy Eller, Patrick De La Garza, Daniel Klein, George Kellerman, Steven Eliscu, Danny Yang
  • Publication number: 20240270870
    Abstract: Disclosed herein are antibodies or antigen binding fragments thereof that bind prostate specific membrane antigen (PSMA), polynucleotides, vectors, host cells, radioconjugates, antibody drug conjugates and methods of treating cancer using the same.
    Type: Application
    Filed: April 10, 2024
    Publication date: August 15, 2024
    Inventors: Shalom Goldberg, Donna Klein, Neeraj Kohli, Theresa Marie McDevitt, Steven J. Orcutt
  • Patent number: 12054534
    Abstract: PSMA binding FN3 domains, their conjugates, isolated nucleotides encoding the molecules, vectors, host cells, and methods of making thereof are useful in the generation of therapeutic molecules and treatment and diagnosis of diseases and disorders.
    Type: Grant
    Filed: October 13, 2020
    Date of Patent: August 6, 2024
    Assignee: Janssen Biotech, Inc.
    Inventors: Rosa Cardoso, Michael Diem, Shalom Goldberg, Linus Hyun, Steven Jacobs, Donna Klein, Karyn O'Neil, Tracy Spinka-Doms
  • Patent number: 12048696
    Abstract: The present invention relates to combinations comprising a positive allosteric modulator (“PAM”) of metabotropic glutamatergic receptor subtype 2 (“mGluR2”) or a pharmaceutically acceptable salt or a solvate thereof, or an orthosteric agonist of metabotropic glutamatergic receptor subtype 2 compound or a pharmaceutically acceptable salt or a solvate thereof, and a synaptic vesicle protein 2A (“SV2A”) ligand.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: July 30, 2024
    Assignee: JANSSEN PHARMACEUTICA NV
    Inventors: Brian D. Klein, Hilde Lavreysen, Stefan Maria Christiaan Pype, Roy E. Twyman, Nancy Eulalie Sylvain Van Osselaer, H. Steven White, Marc André Ceusters, José Maria Cid-Núñez, Andrés Avelino Trabanco-Suárez
  • Publication number: 20240241624
    Abstract: Various embodiments discussed herein enable client applications to be heavily integrated with a voice assistant in order to perform commands associated with voice utterances of users via voice assistant functionality and also seamlessly cause client applications to automatically perform native functions as part of executing the voice utterance. Such heavy integration also allows particular embodiments to support multi-modal input from a user for a single conversational interaction. In this way, client application user interface interactions, such as clicks, touch gestures, or text inputs are executed alternative or in addition to the voice utterances.
    Type: Application
    Filed: March 27, 2024
    Publication date: July 18, 2024
    Inventors: Tudor Buzasu KLEIN, Viktoriya TARANOV, Sergiy GAVRYLENKO, Jaclyn Carley KNAPP, Andrew Paul MCGOVERN, Harris SYED, Chad Steven ESTES, Jesse Daniel Eskes RUSAK, David Ernesto Heekin BURKETT, Allison Anne O'MAHONY, Ashok KUPPUSAMY, Jonathan Reed HARRIS, Jose Miguel Rady ALLENDE, Diego Hernan CARLOMAGNO, Talon Edward IRELAND, Michael Francis PALERMITI, II, Richard Leigh MAINS, Jayant KRISHNAMURTHY
  • Publication number: 20240222288
    Abstract: Integrated circuit (IC) device substrates and structures for mating and aligning with sockets. An IC device may include a frame on and around a substrate, which may include glass or silicon. The frame may include an alignment feature, such as a notch or hole, to mate with a complementary keying feature of a socket. A heat spreader may be coupled to an IC die and extend beyond the substrate or be coupled to the frame. The heat spreader may include a heat pipe. The IC device may be part of an IC system with the device substrate coupled to a system substrate by a socket configured to mate to the frame.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: David Shia, Timothy Gosselin, Aravindha Antoniswamy, Sergio Antonio Chan Arguedas, Elah Bozorg-Grayeli, Johnny Cook, JR., Steven Klein, Rick Canham
  • Patent number: 12009612
    Abstract: Techniques and mechanisms for coupling packaged devices with a socket device. In an embodiment, the socket device comprises a socket body structure and conductors extending therethrough. A pitch of the conductors is in a range of between 0.1 millimeters (mm) and 3 mm. First and second metallization structures also extend, respectively, from opposite respective sides of the socket body structure. In the socket body structure, a conductive shield structure, electrically coupled to the first and second metallization structures, substantially extends around one of the conductors. For each of the first and second metallization structures, a vertical span of the metallization structure is in a range of between 0.05 mm and 2.0 mm, a portion of a side of the metallization structure forms a respective corrugation structure, and a horizontal span of the portion is at least 5% of the vertical span of the metallization structure.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: June 11, 2024
    Assignee: Intel Corporation
    Inventors: Srikant Nekkanty, Steven Klein, Feroz Mohammad, Joe Walczyk, Kuang Liu, Zhichao Zhang
  • Publication number: 20240162134
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 16, 2024
    Inventors: Xiao LU, Jiongxin LU, Christopher COMBS, Alexander HUETTIS, John HARPER, Jieping ZHANG, Nachiket R. RARAVIKAR, Pramod MALATKAR, Steven A. KLEIN, Carl DEPPISCH, Mohit SOOD
  • Publication number: 20240113479
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for socket interconnect structures and related methods. An example socket interconnect apparatus includes a housing defining a plurality of first openings and a plurality of second openings and a ground structure coupled to the housing. The ground structure defines a plurality of third openings. The third openings of the ground structure align with the second openings of the housing when the ground structure is coupled to the housing. A plurality of ground pins are located in respective ones of the second openings and third openings. The ground structure is to electrically couple the ground pins. A plurality of signal pins are located in respective ones of the first openings of the housing. The signal pins are electrically isolated from the ground structure.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Kai Xiao, Phil Geng, Carlos Alberto Lizalde Moreno, Raul Enriquez Shibayama, Steven A. Klein
  • Patent number: 11916322
    Abstract: Techniques and mechanisms for coupling packaged devices with a dual-sided socket device. In an embodiment, two interfaces of the socket device comprise, respectively, first metallization structures and second metallization structures on opposite sides of a socket body structure. The first metallization structures each form a respective corrugation structure to electrically couple with a corresponding conductive contact of a first packaged device. The corrugation structures facilitate such electrical coupling each via a vertical wipe of the corresponding conductive contact. In another embodiment, a pitch of the first metallization structures is in a range of between 0.1 millimeters (mm) and 2 mm. One such metallization structure has a vertical span in a range of between 0.05 mm and 2.0 mm, where a portion of a side of the metallization structure forms a corrugation structure, and has a horizontal span which is at least 5% of the vertical span.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Srikant Nekkanty, Steven Klein, Feroz Mohammad
  • Patent number: 11916003
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Xiao Lu, Jiongxin Lu, Christopher Combs, Alexander Huettis, John Harper, Jieping Zhang, Nachiket R. Raravikar, Pramod Malatkar, Steven A. Klein, Carl Deppisch, Mohit Sood
  • Patent number: 11818832
    Abstract: Embodiments disclosed herein include assemblies. In an embodiment, an assembly comprises a socket and a bolster plate on a board, where the bolster plate has load studs and an opening that surrounds the socket; a shim having first and second ends; and a carrier on the bolster plate, where the carrier has an opening and cutouts. The shim may have an opening through the first end as the second end is affixed to the carrier. The opening of the shim entirely over one cutout from a corner region of the carrier. In an embodiment, the assembly comprises an electronic package in the opening of the carrier, where the electronic package is affixed to the carrier, and a heatsink over the electronic package and carrier, where the first end is directly coupled to a surface of the heatsink and a surface of one load stud of the bolster plate.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: November 14, 2023
    Assignee: Intel Corporation
    Inventors: Feroz Mohammad, Ralph V. Miele, Thomas Boyd, Steven A. Klein, Gregorio R. Murtagian, Eric W. Buddrius, Daniel Neumann, Rolf Laido
  • Patent number: 11789019
    Abstract: The present application discloses proteins or peptides and methods of using such proteins or peptides to evaluate the immune status of a patient. In one embodiment, proteins or peptides may be used to detect endogenous calnexin specific CD4 T cells. In one preferred embodiment, the proteins or peptides may comprise peptide-MHCII tetramers (pMHC tetramers).
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: October 17, 2023
    Assignee: WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Bruce Steven Klein, Marcel Wuethrich
  • Patent number: 11646244
    Abstract: A microprocessor mounting apparatus comprising a microprocessor socket on a printed circuit board (PCB) and a bolster plate surrounding a perimeter of the microprocessor socket. The bolster plate has a first surface adjacent to the PCB, and a second surface opposite the first surface. A heat dissipation device is on the second surface of the bolster plate. The heat dissipation interface is thermally coupled to the microprocessor socket.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 9, 2023
    Assignee: Intel Corporation
    Inventors: Steven A. Klein, Zhimin Wan, Chia-Pin Chiu, Shankar Devasenathipathy
  • Patent number: 11581671
    Abstract: An integrated circuit (IC) socket comprising a housing with a land side, an opposing die side, and sidewalls around a perimeter of the housing. The housing comprises a first dielectric. A plurality of socket pins extends from the land side of the housing through socket pin holes in the housing over the die side of the housing. A second dielectric is within the interstitial regions between the socket pins and sidewalls of the socket pin holes. A frame structure extends around at least a portion of the perimeter of the housing, and a mesh structure is embedded within the first dielectric. The mesh structure has plurality of mesh filaments extending between the plurality of socket pin holes and coupled to the frame structure.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: Zhimin Wan, Steven A. Klein, Chia-Pin Chiu, Shankar Devasenathipathy
  • Patent number: 11569596
    Abstract: Systems, apparatus, and/or processes directed to applying pressure to a socket to alter a shape of the socket to improve a connection between the socket and a substrate, printed circuit board, or other component. The socket may receive one or more chips, may be an interconnect, or may be some other structure that is part of a package. The shape of the socket may be flattened so that a side of the socket may form a high-quality physical and electrical coupling with the substrate.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: January 31, 2023
    Assignee: Intel Corporation
    Inventors: Steven A. Klein, Kuang Liu, Srikant Nekkanty, Feroz Mohammad, Donald Tiendung Tran, Srinivasa Aravamudhan, Hemant Mahesh Shah, Alexander W. Huettis