Patents by Inventor Steven Klein

Steven Klein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250116154
    Abstract: An electronic door system includes a door frame, a door hingedly coupled to the door frame, an electrically-controllable component coupled to or disposed within the door, a door wiring harness, and a cover. The door defines a channel extending along at least a portion of a peripheral edge thereof. The door wiring harness includes a wire extending along and within the channel. The wire is coupled to the electrically-controllable component. The cover extends along the peripheral edge and covers the channel.
    Type: Application
    Filed: June 30, 2023
    Publication date: April 10, 2025
    Applicant: Therma-Tru Corporation
    Inventors: Nicholas Fink, May Russell, Brett Finley, Jacob Weil, Daniel Schneider, Keith Butcher, Logan Harvey, Brandon Knoll, Andrew Waite, Ben Kowalski, Ryan Starling, Frances Wang, Joseph Gonzalez, David Hezlep, Steven Orchosky, Hidekazu Saegusa, Videl Smith, Bill Klein, Adam Allmandinger, Tim Quirin, Jon Klein, John Burleson, Kevin Anderson, Brian Frackelton, Todd Whitaker, George Polly, Arlber Chang, Derek Fielding
  • Publication number: 20250112392
    Abstract: A semiconductor package carrier used to support a semiconductor package (e.g., a semiconductor, a microprocessor, etc.) as the semiconductor package is moved from a shipping tray to a land grid array (LGA) socket during assembly of an electronic device. The semiconductor package carrier including a carrier body including a plurality of support structures arranged to support a portion of the semiconductor package. The semiconductor package carrier further including a locking structure moveable between a first position and a second position, wherein the first position allows the support structures to receive the semiconductor package and the second position secures the semiconductor package to the carrier body. In some embodiments, the semiconductor package carrier may also include a thermal interface material (TIM) breaker to facilitate removal of a heatsink from the semiconductor package. Other embodiments are described and claimed.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Richard Canham, Ernesto Borboa Lizarraga, Daniel Neumann, Shelby Ferguson, Eric Buddrius, Hardikkumar Prajapati, Kirk Wheeler, Steven Klein, Shaun Immeker, Jeffory L. Smalley
  • Publication number: 20250082749
    Abstract: A Dectin-2 ligand vaccine adjuvant and a method of making and using the Dectin-2 ligand vaccine adjuvant in a vaccine to immunize a patient are disclosed. Also discloses is a vaccine composition comprising a Bl-Eng2 antigen and methods of using the vaccine composition to immunize a subject against a fungal infection.
    Type: Application
    Filed: August 19, 2024
    Publication date: March 13, 2025
    Inventors: Bruce Steven Klein, Huafeng Wang, Marcel Wuethrich, Tristan Theodore Brandhorst
  • Publication number: 20250080603
    Abstract: A method and system for centralized control of user devices is disclosed. The method for centralized control of user devices via universal IP services registrar includes receiving a request to register a user device for a plurality of services, registering the user device for the plurality of services by creating a user settings profile for the user for each of the plurality of services, receiving data from the plurality of registered services, and transmitting received data to the user device in accordance with the user profile.
    Type: Application
    Filed: November 20, 2024
    Publication date: March 6, 2025
    Applicant: AT&T Intellectual Property I, L.P.
    Inventors: Steven A. Siegel, Reuben Klein, Leopold B. Strahs
  • Publication number: 20250055217
    Abstract: A Land Grid Array (LGA) interface assembly used to physically interface or connect a semiconductor package (e.g., a semiconductor, a microprocessor, etc.) and a PCB, motherboard, etc. The LGA interface assembly including an LGA socket including a plurality of socket pins arranged and configured to contact a plurality of contact pads on the semiconductor package to enable data transfer. The socket pins including a multi-bend and/or zig-zag configuration arranged and configured to minimize lateral displacement of the socket pin relative to the contact pad during insertion of the semiconductor package into the LGA socket. Other embodiments are described and claimed.
    Type: Application
    Filed: October 28, 2024
    Publication date: February 13, 2025
    Applicant: Intel Corporation
    Inventors: Min Pei, Lejie Liu, Ralph Miele, Phil Geng, Steven Klein
  • Publication number: 20250041301
    Abstract: The present invention relates to combinations comprising a positive allosteric modulator (“PAM”) of metabotropic glutamatergic receptor subtype 2 (“mGluR2”) or a pharmaceutically acceptable salt or a solvate thereof, or an orthosteric agonist of metabotropic glutamatergic receptor subtype 2 compound or a pharmaceutically acceptable salt or a solvate thereof, and a synaptic vesicle protein 2A (“SV2A”) ligand.
    Type: Application
    Filed: July 29, 2024
    Publication date: February 6, 2025
    Applicant: JANSSEN PHARMACEUTICA NV
    Inventors: Brian D. KLEIN, Hilde LAVREYSEN, Stefan Maria, Christiaan PYPE, Roy E. TWYMAN, Nancy Eulalie, Sylvain VAN OSSELAER, H. Steven WHITE, Marc André CEUSTERS, José Maria CID-NÚÑEZ, Andrés Avelino TRABANCO-SUÁREZ, Roger Francis BONE
  • Patent number: 12127363
    Abstract: Embodiments disclosed herein include sockets and electronic packages with socket architectures. In an embodiment, a socket comprises a housing with a first surface and a second surface. In an embodiment, a plurality of interconnect pins pass through the housing. In an embodiment, an alignment hole is provided through the housing. In an embodiment, an alignment post extending out from the first surface of the housing is also provided.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: October 22, 2024
    Assignee: Intel Corporation
    Inventors: Feifei Cheng, Thomas Boyd, Kuang Liu, Steven A. Klein, Daniel Neumann, Mohanraj Prabhugoud
  • Patent number: 12097258
    Abstract: A Dectin-2 ligand vaccine adjuvant and a method of making and using the Dectin-2 ligand vaccine adjuvant in a vaccine to immunize a patient are disclosed. Also discloses is a vaccine composition comprising a Bl-Eng2 antigen and methods of using the vaccine composition to immunize a subject against a fungal infection.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: September 24, 2024
    Assignee: WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Bruce Steven Klein, Huafeng Wang, Marcel Wuethrich, Tristan Theodore Brandhorst
  • Publication number: 20240297119
    Abstract: An electronic device (100, 800, 1000) and associated methods are disclosed. In one example, the electronic device (100, 800, 1000) includes an interconnect socket (102, 302, 402, 802, 1004, 1320, 1402, 1506) that includes a liquid metal. In selected examples, the interconnect socket (102, 302, 402) includes a resilient material spacer (130, 230, 330, 430) located between pins (110, 210, 310, 410) in an array of pins (110, 210, 310, 410). In selected examples, the electronic device (1000) includes configurations to aid in de-socketing.
    Type: Application
    Filed: December 22, 2021
    Publication date: September 5, 2024
    Inventors: Srikant Nekkanty, Karumbu Meyyappan, Andres Ramirez Macias, Zhe Chen, Jeffory L. Smalley, Zhichao Zhang, Steven A. Klein, Eric Erike
  • Publication number: 20240222288
    Abstract: Integrated circuit (IC) device substrates and structures for mating and aligning with sockets. An IC device may include a frame on and around a substrate, which may include glass or silicon. The frame may include an alignment feature, such as a notch or hole, to mate with a complementary keying feature of a socket. A heat spreader may be coupled to an IC die and extend beyond the substrate or be coupled to the frame. The heat spreader may include a heat pipe. The IC device may be part of an IC system with the device substrate coupled to a system substrate by a socket configured to mate to the frame.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Applicant: Intel Corporation
    Inventors: David Shia, Timothy Gosselin, Aravindha Antoniswamy, Sergio Antonio Chan Arguedas, Elah Bozorg-Grayeli, Johnny Cook, JR., Steven Klein, Rick Canham
  • Patent number: 12009612
    Abstract: Techniques and mechanisms for coupling packaged devices with a socket device. In an embodiment, the socket device comprises a socket body structure and conductors extending therethrough. A pitch of the conductors is in a range of between 0.1 millimeters (mm) and 3 mm. First and second metallization structures also extend, respectively, from opposite respective sides of the socket body structure. In the socket body structure, a conductive shield structure, electrically coupled to the first and second metallization structures, substantially extends around one of the conductors. For each of the first and second metallization structures, a vertical span of the metallization structure is in a range of between 0.05 mm and 2.0 mm, a portion of a side of the metallization structure forms a respective corrugation structure, and a horizontal span of the portion is at least 5% of the vertical span of the metallization structure.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: June 11, 2024
    Assignee: Intel Corporation
    Inventors: Srikant Nekkanty, Steven Klein, Feroz Mohammad, Joe Walczyk, Kuang Liu, Zhichao Zhang
  • Publication number: 20240162134
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.
    Type: Application
    Filed: January 19, 2024
    Publication date: May 16, 2024
    Inventors: Xiao LU, Jiongxin LU, Christopher COMBS, Alexander HUETTIS, John HARPER, Jieping ZHANG, Nachiket R. RARAVIKAR, Pramod MALATKAR, Steven A. KLEIN, Carl DEPPISCH, Mohit SOOD
  • Publication number: 20240113479
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for socket interconnect structures and related methods. An example socket interconnect apparatus includes a housing defining a plurality of first openings and a plurality of second openings and a ground structure coupled to the housing. The ground structure defines a plurality of third openings. The third openings of the ground structure align with the second openings of the housing when the ground structure is coupled to the housing. A plurality of ground pins are located in respective ones of the second openings and third openings. The ground structure is to electrically couple the ground pins. A plurality of signal pins are located in respective ones of the first openings of the housing. The signal pins are electrically isolated from the ground structure.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Kai Xiao, Phil Geng, Carlos Alberto Lizalde Moreno, Raul Enriquez Shibayama, Steven A. Klein
  • Patent number: 11916322
    Abstract: Techniques and mechanisms for coupling packaged devices with a dual-sided socket device. In an embodiment, two interfaces of the socket device comprise, respectively, first metallization structures and second metallization structures on opposite sides of a socket body structure. The first metallization structures each form a respective corrugation structure to electrically couple with a corresponding conductive contact of a first packaged device. The corrugation structures facilitate such electrical coupling each via a vertical wipe of the corresponding conductive contact. In another embodiment, a pitch of the first metallization structures is in a range of between 0.1 millimeters (mm) and 2 mm. One such metallization structure has a vertical span in a range of between 0.05 mm and 2.0 mm, where a portion of a side of the metallization structure forms a corrugation structure, and has a horizontal span which is at least 5% of the vertical span.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Srikant Nekkanty, Steven Klein, Feroz Mohammad
  • Patent number: 11916003
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: February 27, 2024
    Assignee: Intel Corporation
    Inventors: Xiao Lu, Jiongxin Lu, Christopher Combs, Alexander Huettis, John Harper, Jieping Zhang, Nachiket R. Raravikar, Pramod Malatkar, Steven A. Klein, Carl Deppisch, Mohit Sood
  • Patent number: 11818832
    Abstract: Embodiments disclosed herein include assemblies. In an embodiment, an assembly comprises a socket and a bolster plate on a board, where the bolster plate has load studs and an opening that surrounds the socket; a shim having first and second ends; and a carrier on the bolster plate, where the carrier has an opening and cutouts. The shim may have an opening through the first end as the second end is affixed to the carrier. The opening of the shim entirely over one cutout from a corner region of the carrier. In an embodiment, the assembly comprises an electronic package in the opening of the carrier, where the electronic package is affixed to the carrier, and a heatsink over the electronic package and carrier, where the first end is directly coupled to a surface of the heatsink and a surface of one load stud of the bolster plate.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: November 14, 2023
    Assignee: Intel Corporation
    Inventors: Feroz Mohammad, Ralph V. Miele, Thomas Boyd, Steven A. Klein, Gregorio R. Murtagian, Eric W. Buddrius, Daniel Neumann, Rolf Laido
  • Patent number: 11789019
    Abstract: The present application discloses proteins or peptides and methods of using such proteins or peptides to evaluate the immune status of a patient. In one embodiment, proteins or peptides may be used to detect endogenous calnexin specific CD4 T cells. In one preferred embodiment, the proteins or peptides may comprise peptide-MHCII tetramers (pMHC tetramers).
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: October 17, 2023
    Assignee: WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Bruce Steven Klein, Marcel Wuethrich
  • Patent number: 11646244
    Abstract: A microprocessor mounting apparatus comprising a microprocessor socket on a printed circuit board (PCB) and a bolster plate surrounding a perimeter of the microprocessor socket. The bolster plate has a first surface adjacent to the PCB, and a second surface opposite the first surface. A heat dissipation device is on the second surface of the bolster plate. The heat dissipation interface is thermally coupled to the microprocessor socket.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 9, 2023
    Assignee: Intel Corporation
    Inventors: Steven A. Klein, Zhimin Wan, Chia-Pin Chiu, Shankar Devasenathipathy
  • Patent number: 11581671
    Abstract: An integrated circuit (IC) socket comprising a housing with a land side, an opposing die side, and sidewalls around a perimeter of the housing. The housing comprises a first dielectric. A plurality of socket pins extends from the land side of the housing through socket pin holes in the housing over the die side of the housing. A second dielectric is within the interstitial regions between the socket pins and sidewalls of the socket pin holes. A frame structure extends around at least a portion of the perimeter of the housing, and a mesh structure is embedded within the first dielectric. The mesh structure has plurality of mesh filaments extending between the plurality of socket pin holes and coupled to the frame structure.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: Zhimin Wan, Steven A. Klein, Chia-Pin Chiu, Shankar Devasenathipathy
  • Patent number: 11569596
    Abstract: Systems, apparatus, and/or processes directed to applying pressure to a socket to alter a shape of the socket to improve a connection between the socket and a substrate, printed circuit board, or other component. The socket may receive one or more chips, may be an interconnect, or may be some other structure that is part of a package. The shape of the socket may be flattened so that a side of the socket may form a high-quality physical and electrical coupling with the substrate.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: January 31, 2023
    Assignee: Intel Corporation
    Inventors: Steven A. Klein, Kuang Liu, Srikant Nekkanty, Feroz Mohammad, Donald Tiendung Tran, Srinivasa Aravamudhan, Hemant Mahesh Shah, Alexander W. Huettis