Abstract: The present invention provides a method for verifying interconnected blocks in a top-block by creating one or more assertions for each input/output of one or more blocks to be used within the top-block, creating one or more assertions for each input/output of the top-block, providing a stimulus intended to cause each assertion to be triggered, and verifying that a result for each assertion was correct. The assertions verify that a valid functional mode caused a change in an output or a valid functional mode received the change in an input. A computer program embodied on a computer readable medium can implement the foregoing steps as one or more code segments.