Patents by Inventor Steven Kosier
Steven Kosier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10746817Abstract: A structure having collocated magnetic field sensing elements can be used to simultaneously determine magnetic field and mechanical stress. A primary magnetic field sensing element generates a primary signal responsive to a magnetic field and a secondary magnetic field sensing element generates a secondary signal responsive to mechanical stress. A system includes a stress compensation module to receive the primary and signals, and to compensate for mechanical stress in the primary signal.Type: GrantFiled: November 9, 2017Date of Patent: August 18, 2020Assignee: Allegro MicroSystems, LLCInventors: Steven Kosier, Gregory Delmain
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Patent number: 10580861Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.Type: GrantFiled: February 20, 2018Date of Patent: March 3, 2020Assignees: POLAR SEMICONDUCTOR, LLC, SANKEN ELECTRIC CO., LTD.Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven Kosier, Peter West
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Patent number: 10153366Abstract: Apparatus and associated methods relate to controlling an electric field profile within a drift region of an LDMOS device using first and second RESURF regions. The first RESURF region extends from a source end toward a drain end of the LDMOS device. The first RESURF region is adjacent to a forms a metallurgical junction with the drift region. The second RESURF layer extends from the drain end toward the source end of the LDMOS device. The second RESURF layer has an end that is longitudinally between the body contact and the source end of the first RESURF layer. A distance between the end of the second RESURF layer and the body contact is greater than a vertical distance between the end of the second RESURF layer and the body contact. A maximum electric field between the second RESURF layer and the body contact can be advantageously reduced with this geometry.Type: GrantFiled: March 9, 2016Date of Patent: December 11, 2018Assignee: Polar Semiconductor, LLCInventors: Thomas S. Chung, Noel Hoillien, Peter N. Manos, Steven Kosier
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Patent number: 10141440Abstract: Apparatus and associated methods relate to controlling an electric field profile within a drift region of an LDMOS device using biased field plates to deplete majority carriers from a drift region between a body/drift-region metallurgical junction and a drain contact. Such field plates are located in trenches that longitudinally extend within the drift region. Field plates are laterally spaced apart from each other at a distance that permits substantial depletion of majority carriers between adjacent field plates. Trenches have trench bottoms located within a drift-region/substrate metallurgical junction so as to permit substantial depletion of majority carriers between trench bottoms and the drift-region/substrate metallurgical junction. Between adjacent trenches, dopant concentrations can be increased up to a threshold that can be substantially depleted under specified bias conditions.Type: GrantFiled: March 9, 2016Date of Patent: November 27, 2018Assignee: Polar Semiconductor, LLCInventors: Steven Kosier, Thomas Chung
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Publication number: 20180321329Abstract: A structure having collocated magnetic field sensing elements can be used to simultaneously determine magnetic field and mechanical stress. A primary magnetic field sensing element generates a primary signal responsive to a magnetic field and a secondary magnetic field sensing element generates a secondary signal responsive to mechanical stress. A system includes a stress compensation module to receive the primary and signals, and to compensate for mechanical stress in the primary signal.Type: ApplicationFiled: November 9, 2017Publication date: November 8, 2018Applicant: Allegro MicroSystems, LLCInventors: Steven Kosier, Gregory Delmain
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Publication number: 20180175146Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.Type: ApplicationFiled: February 20, 2018Publication date: June 21, 2018Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven Kosier, Peter West
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Patent number: 9899343Abstract: Apparatus and associated methods relate to a bonding pad structure for a trench-based semiconductor device. The bonding pad structure reduces a peak magnitude of the electric field between a metal bonding pad and the underlying semiconductor. The bonding pad structure includes a plurality of trenches vertically extending from a top surface of a semiconductor. Each of the plurality of trenches has dielectric sidewalls and a dielectric bottom, the dielectric sidewalls and dielectric bottom electrically isolating a conductive core within each of the trenches from a region of semiconductor outside of and adjacent to each of the plurality of trenches. The bonding pad structure includes a metal bonding pad disposed above the plurality of trenches, the metal bonding pad electrically isolated from the region of semiconductor outside of the trenches. The conductive core can be biased to reduce the magnitude of the field between adjacent trenches.Type: GrantFiled: March 9, 2016Date of Patent: February 20, 2018Assignees: Polar Semiconductor, LLC, SANKEN ELECTRIC CO., LTD.Inventors: Peter West, Steven Kosier, Tatsuya Kamimura, Don Rankila
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Patent number: 9851417Abstract: A structure having collocated magnetic field sensing elements can be used to simultaneously determine magnetic field and mechanical stress. A primary magnetic field sensing element generates a primary signal responsive to a magnetic field and a secondary magnetic field sensing element generates a secondary signal responsive to mechanical stress. A system includes a stress compensation module to receive the primary and signals, and to compensate for mechanical stress in the primary signal.Type: GrantFiled: July 28, 2015Date of Patent: December 26, 2017Assignee: Allegro MicroSystems, LLCInventors: Steven Kosier, Gregory Delmain
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Patent number: 9818828Abstract: Apparatus and associated methods relate to an edge-termination structure surrounding a high-voltage MOSFET for reducing a peak lateral electric field. The edge-termination structure includes a sequence of annular trenches and semiconductor pillars circumscribing the high-voltage MOSFET. Each of the annular trenches is laterally separated from the other annular trenches by one of the semiconductor pillars. Each of the annular trenches has dielectric sidewalls and a dielectric bottom electrically isolating a conductive core within each of the annular trenches from a drain-biased region of the semiconductor pillar outside of and adjacent to the annular trench. The conductive core of the innermost trench is biased, while the conductive cores of one or more outer trenches are floating. In some embodiments, a surface of an inner semiconductor pillar is biased as well. The peak lateral electric field can advantageously be reduced by physical arrangement of trenches and electrical biasing sequence.Type: GrantFiled: March 9, 2016Date of Patent: November 14, 2017Assignees: POLAR SEMICONDUCTOR, LLC, SANKEN ELECTRIC CO., LTD.Inventors: Peter West, Steven Kosier, Tatsuya Kamimura, Don Rankila
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Publication number: 20170263580Abstract: Apparatus and associated methods relate to a bonding pad structure for a trench-based semiconductor device. The bonding pad structure reduces a peak magnitude of the electric field between a metal bonding pad and the underlying semiconductor. The bonding pad structure includes a plurality of trenches vertically extending from a top surface of a semiconductor. Each of the plurality of trenches has dielectric sidewalls and a dielectric bottom, the dielectric sidewalls and dielectric bottom electrically isolating a conductive core within each of the trenches from a region of semiconductor outside of and adjacent to each of the plurality of trenches. The bonding pad structure includes a metal bonding pad disposed above the plurality of trenches, the metal bonding pad electrically isolated from the region of semiconductor outside of the trenches. The conductive core can be biased to reduce the magnitude of the field between adjacent trenches.Type: ApplicationFiled: March 9, 2016Publication date: September 14, 2017Inventors: Peter West, Steven Kosier, Tatsuya Kamimura, Don Rankila
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Publication number: 20170263765Abstract: Apparatus and associated methods relate to controlling an electric field profile within a drift region of an LDMOS device using biased field plates to deplete majority carriers from a drift region between a body/drift-region metallurgical junction and a drain contact. Such field plates are located in trenches that longitudinally extend within the drift region. Field plates are laterally spaced apart from each other at a distance that permits substantial depletion of majority carriers between adjacent field plates. Trenches have trench bottoms located within a drift-region/substrate metallurgical junction so as to permit substantial depletion of majority carriers between trench bottoms and the drift-region/substrate metallurgical junction. Between adjacent trenches, dopant concentrations can be increased up to a threshold that can be substantially depleted under specified bias conditions.Type: ApplicationFiled: March 9, 2016Publication date: September 14, 2017Inventors: Steven Kosier, Thomas Chung
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Publication number: 20170263759Abstract: Apparatus and associated methods relate to controlling an electric field profile within a drift region of an LDMOS device using first and second RESURF regions. The first RESURF region extends from a source end toward a drain end of the LDMOS device. The first RESURF region is adjacent to a forms a metallurgical junction with the drift region. The second RESURF layer extends from the drain end toward the source end of the LDMOS device. The second RESURF layer has an end that is longitudinally between the body contact and the source end of the first RESURF layer. A distance between the end of the second RESURF layer and the body contact is greater than a vertical distance between the end of the second RESURF layer and the body contact. A maximum electric field between the second RESURF layer and the body contact can be advantageously reduced with this geometry.Type: ApplicationFiled: March 9, 2016Publication date: September 14, 2017Inventors: Thomas S. Chung, Noel Hoillien, Peter N. Manos, Steven Kosier
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Publication number: 20170263718Abstract: Apparatus and associated methods relate to an edge-termination structure surrounding a high-voltage MOSFET for reducing a peak lateral electric field. The edge-termination structure includes a sequence of annular trenches and semiconductor pillars circumscribing the high-voltage MOSFET. Each of the annular trenches is laterally separated from the other annular trenches by one of the semiconductor pillars. Each of the annular trenches has dielectric sidewalls and a dielectric bottom electrically isolating a conductive core within each of the annular trenches from a drain-biased region of the semiconductor pillar outside of and adjacent to the annular trench. The conductive core of the innermost trench is biased, while the conductive cores of one or more outer trenches are floating. In some embodiments, a surface of an inner semiconductor pillar is biased as well. The peak lateral electric field can advantageously be reduced by physical arrangement of trenches and electrical biasing sequence.Type: ApplicationFiled: March 9, 2016Publication date: September 14, 2017Inventors: Peter West, Steven Kosier, Tatsuya Kamimura, Don Rankila
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Patent number: 9735345Abstract: In one aspect, a vertical Hall effect sensor includes a semiconductor wafer having a first conductivity type and a plurality of semiconductive electrodes disposed on the semiconductor wafer. The plurality of semiconductive electrodes have the first conductivity type and include a source electrode, a first sensing electrode and a second sensing electrode, arranged such that the source electrode is between the first sensing electrode and the sensing electrode and a first drain electrode and a second drain electrode, arranged such that the first sensing electrode, second sensing electrode, and source electrode are between the first drain electrode and the second drain electrode. The vertical Hall effect sensor also includes a plurality of semiconductor fingers disposed on the semiconductor wafer and interdigitated with the plurality of semiconductive electrodes, the semiconductor fingers having a second conductivity type.Type: GrantFiled: March 4, 2016Date of Patent: August 15, 2017Assignee: Allegro MicroSystems, LLCInventors: Steven Kosier, Noel Hoilien
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Publication number: 20170194485Abstract: A power metal-oxide semiconductor field-effect transistor (MOSFET) and method of manufacturing thereof, includes a trench, a trench doping and a pillar doping region. The trench is etched into a silicon layer that includes a gate structure disposed therein. The trench doping is implanted in the silicon layer vertically below the trench and has an opposite doping type than the silicon layer. The pillar doping region is implanted in the silicon layer vertically below, and spaced from the trench doping. The pillar doping region has a same doping type as the trench doping.Type: ApplicationFiled: January 6, 2016Publication date: July 6, 2017Inventors: Christopher Smith, Steven Kosier, Peter West
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Publication number: 20170030980Abstract: A structure having collocated magnetic field sensing elements can be used to simultaneously determine magnetic field and mechanical stress. A primary magnetic field sensing element generates a primary signal responsive to a magnetic field and a secondary magnetic field sensing element generates a secondary signal responsive to mechanical stress. A system includes a stress compensation module to receive the primary and signals, and to compensate for mechanical stress in the primary signal.Type: ApplicationFiled: July 28, 2015Publication date: February 2, 2017Applicant: Allegro Microsystems, LLCInventors: Steven Kosier, Gregory Delmain
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Publication number: 20160247879Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern including a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.Type: ApplicationFiled: February 23, 2016Publication date: August 25, 2016Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven Kosier, Peter West
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Publication number: 20160190433Abstract: In one aspect, a vertical Hall effect sensor includes a semiconductor wafer having a first conductivity type and a plurality of semiconductive electrodes disposed on the semiconductor wafer. The plurality of semiconductive electrodes have the first conductivity type and include a source electrode, a first sensing electrode and a second sensing electrode, arranged such that the source electrode is between the first sensing electrode and the sensing electrode and a first drain electrode and a second drain electrode, arranged such that the first sensing electrode, second sensing electrode, and source electrode are between the first drain electrode and the second drain electrode. The vertical Hall effect sensor also includes a plurality of semiconductor fingers disposed on the semiconductor wafer and interdigitated with the plurality of semiconductive electrodes, the semiconductor fingers having a second conductivity type.Type: ApplicationFiled: March 4, 2016Publication date: June 30, 2016Applicant: Allegro Microsystems, LLCInventors: Steven Kosier, Noel Hoilien
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Patent number: 9312473Abstract: In one aspect, a vertical Hall effect sensor includes a semiconductor wafer having a first conductivity type and a plurality of semiconductive electrodes disposed on the semiconductor wafer. The plurality of semiconductive electrodes have the first conductivity type and include a source electrode, a first sensing electrode and a second sensing electrode, arranged such that the source electrode is between the first sensing electrode and the sensing electrode and a first drain electrode and a second drain electrode, arranged such that the first sensing electrode, second sensing electrode, and source electrode are between the first drain electrode and the second drain electrode. The vertical Hall effect sensor also includes a plurality of semiconductor fingers disposed on the semiconductor wafer and interdigitated with the plurality of semiconductive electrodes, the semiconductor fingers having a second conductivity type.Type: GrantFiled: September 30, 2013Date of Patent: April 12, 2016Assignee: Allegro Microsystems, LLCInventors: Steven Kosier, Noel Hoilien
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Patent number: 9013838Abstract: Novel anisotropic magneto-resistive (AMR) sensor architectures and techniques for fabricating same are described. In at least one embodiment, an AMR sensor is provided that includes barber pole structures having upper and low metal layers that are formed of different materials. The metal material closer to the AMR element is formed of a material that can be etched using an etching process that does not attack the AMR material. In some other embodiments, AMR sensors having segmented AMR sensing elements are described.Type: GrantFiled: October 1, 2013Date of Patent: April 21, 2015Assignee: Allegro Microsystems, LLCInventors: David G. Erie, Joseph Burkhardt, Steven Kosier