Abstract: A digital signal processor implementation of three algorithms used to detect high impedance faults. The algorithms can be wavelet based, higher order statistics based and neural network based. The algorithms are modified to process one second of data instead of ten seconds of data and a double buffered acquisition is connected to the output of the algorithms.

Abstract: An apparatus, system, and method for detecting high impedance faults in electrical power lines using a composite high impedance fault detection system having a voter logic that samples the logical outputs from a plurality of independent high impedance detection systems and determines a high impedance fault if any two of the plurality of independent high impedance detection systems indicates a high impedance fault. Preferably, the plurality of high impedance detection systems include a wavelet based high impedance fault detection system having a first logical output, a higher order statistics based high impedance fault detection system having a second logical output, and a neural net based high impedance fault detection system having a third logical output. Preferably, each of the plurality of high impedance fault detection systems includes an independent high impedance fault detection application that independently detects a high impedance fault on the electrical power line.