Patents by Inventor Steven L. Belt
Steven L. Belt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Information handling system with processing system, low-power processing system and shared resources
Patent number: 8799695Abstract: An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.Type: GrantFiled: August 16, 2012Date of Patent: August 5, 2014Assignee: Dell Products, LPInventors: Steven L. Belt, Andrew T. Sultenfuss -
Information Handling System with Processing System, Low-power Processing System and Shared Resources
Publication number: 20120311364Abstract: An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.Type: ApplicationFiled: August 16, 2012Publication date: December 6, 2012Applicant: DELL PRODUCTS, LPInventors: Steven L. Belt, Andrew T. Sultenfuss -
Information handling system with processing system, low-power processing system and shared resources
Patent number: 8271817Abstract: An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.Type: GrantFiled: September 23, 2011Date of Patent: September 18, 2012Assignee: Dell Products, LPInventors: Steven L. Belt, Andrew T. Sultenfuss -
Information Handling System with Processing System, Low-power Processing System and Shared Resources
Publication number: 20120013795Abstract: An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.Type: ApplicationFiled: September 23, 2011Publication date: January 19, 2012Applicant: DELL PRODUCTS, LPInventors: Steven L. Belt, Andrew T. Sultenfuss -
Information handling system with processing system, low-power processing system and shared resources
Patent number: 8037333Abstract: An information handling system employs low-power processing. In a particular form, an information handling system can include a processing system configured operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system. The information handling system can also include a low-power processing system configured to access the shared resource of the processing system during operation of the low-power processing system. The operation of the low-power processing system can be separate from the operation of the processing system. The information handling system can also include a chipset including a processor of the processing system and operable to be enabled during operation of the processing system. The processor can be configured to be disabled during operation of the low-power processing system.Type: GrantFiled: October 31, 2008Date of Patent: October 11, 2011Assignee: Dell Products, LPInventors: Steven L. Belt, Andrew T. Sultenfuss -
Publication number: 20100115313Abstract: An information handling system employs low-power processing. In a particular form, an information handling system can include a processing system configured operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system. The information handling system can also include a low-power processing system configured to access the shared resource of the processing system during operation of the low-power processing system. The operation of the low-power processing system can be separate from the operation of the processing system. The information handling system can also include a chipset including a processor of the processing system and operable to be enabled during operation of the processing system. The processor can be configured to be disabled during operation of the low-power processing system.Type: ApplicationFiled: October 31, 2008Publication date: May 6, 2010Applicant: DELL PRODUCTS, LPInventors: Steven L. Belt, Andrew T. Sultenfuss
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Patent number: 6499086Abstract: A dedicated bus between a central processing unit and a peripheral unit, such as a graphics controller driving a video display, provides enhanced capability in an environment in which signal processing occurs within the central processing unit. The dedicated bus relieves other data buses, such as the PCI bus, of the need to communicate large amounts of data, such as decompressed video data. The resulting system supports high bandwidth transmissions of decompressed video data, enabling high resolution 24 bit full motion video and multiple data stream video.Type: GrantFiled: January 29, 2001Date of Patent: December 24, 2002Assignee: Advanced Micro Devices Inc.Inventors: Steven L. Belt, Douglas D. Gephardt, Drew J. Dutton, Brett B. Stewart, Rita M. Wisor
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Patent number: 6378068Abstract: A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. When running a multi-tasking operating system where an application program is being executed in a restricted mode, a suspend/resume operation can be carried out in which the system is substantially powered down and then powered back up, and will resume the interrupted application with the restricted mode back in effect. Further, set-up changes such as adjustment of the processor speed can be made without exiting the application program running in the restricted mode.Type: GrantFiled: June 1, 1995Date of Patent: April 23, 2002Assignee: NEC CorporationInventors: Mark J. Foster, Saifuddin T. Fakhruddin, James L. Walker, Matthew B. Mendelow, Jiming Sun, Rodman S. Brahman, Michael P. Krau, Brian D. Willoughby, Michael D. Maddix, Steven L. Belt, Scott A. Hovey, Mark A. Ruthenbeck
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Patent number: 6301673Abstract: A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. When running a multi-tasking operating system where an application program is being executed in a restricted mode, a suspend/resume operation can be carried out in which the system is substantially powered down and then powered back up, and will resume the interrupted application with the restricted mode back in effect. Further, set-up changes such as adjustment of the processor speed can be made without exiting the application program running in the restricted mode.Type: GrantFiled: January 23, 1997Date of Patent: October 9, 2001Assignee: NEC CorporationInventors: Mark J. Foster, Saifuddin T. Fakhruddin, James L. Walker, Matthew B. Mendelow, Jiming Sun, Rodman S. Brahman, Michael P. Krau, Brian D. Willoughby, Michael D. Maddix, Steven L. Belt, Scott A. Hovey, Mark A. Ruthenbeck
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Publication number: 20010004750Abstract: A dedicated bus between a central processing unit and a peripheral unit, such as a graphics controller driving a video display, provides enhanced capability in an environment in which signal processing occurs within the central processing unit. The dedicated bus relieves other data buses, such as the PCI bus, of the need to communicate large amounts of data, such as decompressed video data. The resulting system supports high bandwidth transmissions of decompressed video data, enabling high resolution 24 bit full motion video and multiple data stream video.Type: ApplicationFiled: January 29, 2001Publication date: June 21, 2001Inventors: Steven L. Belt, Douglas D. Gephardt, Drew J. Dutton, Brett B. Stewart, Rita M. Wisor
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Patent number: 6223293Abstract: A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. When running a multi-tasking operating system where an application program is being executed in a restricted mode, a suspend/resume operation can be carried out in which the system is substantially powered down and then powered back up, and will resume the interrupted application with the restricted mode back in effect. Further, setup changes such as adjustment of the processor speed can be made without exiting the application program running in the restricted mode.Type: GrantFiled: February 16, 1995Date of Patent: April 24, 2001Assignee: NEC CorporationInventors: Mark J. Foster, Saifuddin T. Fakhruddin, James L. Walker, Matthew B. Mendelow, Jiming Sun, Rodman S. Brahman, Michael P. Krau, Brian D. Willoughby, Michael D. Maddix, Steven L. Belt, Scott A. Hovey, Mark A. Ruthenbeck
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Patent number: 6219754Abstract: A dedicated bus between a central processing unit and a peripheral unit, such as a graphics controller driving a video display, provides enhanced capability in an environment in which signal processing occurs within the central processing unit. The dedicated bus relieves other data buses, such as the PCI bus, of the need to communicate large amounts of data, such as decompressed video data. The resulting system supports high bandwidth transmissions of decompressed video data, enabling high resolution 24 bit full motion video and multiple data stream video.Type: GrantFiled: December 19, 1997Date of Patent: April 17, 2001Assignee: Advanced Micro Devices Inc.Inventors: Steven L. Belt, Douglas D. Gephardt, Drew J. Dutton, Brett B. Stewart, Rita M. Wisor
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Patent number: 6193422Abstract: A portable computer system includes an input device such as a keyboard, a display, and a processor which is operable in a normal operational mode and in a reduced power mode, the processor carrying out program execution in each of the normal operational mode and reduced power mode. A timing arrangement switches the processor from its normal operational mode to its reduced power mode in response to the absence of any of a plurality of predetermined events during a predetermined time interval, the predetermined events including actuation of keys on the keyboard and transmission of information to the video display.Type: GrantFiled: June 22, 1994Date of Patent: February 27, 2001Assignee: NEC CorporationInventors: Steven L. Belt, Robert J. Grabon, Chandrakant H. Pandya, Jiming Sun, Neysa K. Terry-Gray, Min E. Lee, Norman M. Hack
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Patent number: 5948093Abstract: An interrupt polling unit included within a bus interface unit of a microprocessor is provided. The interrupt polling unit causes an interrupt acknowledge bus transaction to occur. If an interrupt controller receiving the interrupt acknowledge bus transaction returns an interrupt vector indicative of an interrupt service routine, then the microprocessor executes the interrupt service routine. The number of interrupt acknowledge bus transactions associated with the interrupt is reduced from two to one. In one embodiment, the interrupt polling unit causes an interrupt acknowledge bus transaction to occur when the microprocessor is performing a task switch. The task switch may be performed by hardware included within the microprocessor or, alternatively, by software executing upon the microprocessor.Type: GrantFiled: February 9, 1996Date of Patent: September 7, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Scott E. Swanstrom, David S. Christie, Steven L. Belt
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Patent number: 5903766Abstract: A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. When running a multi-tasking operating system where an application program is being executed in a restricted mode, a suspend/resume operation can be carried out in which the system is substantially powered down and then powered back up, and will resume the interrupted application with the restricted mode back in effect. Further, set-up changes such as adjustment of the processor speed can be made without exiting the application program running in the restricted mode.Type: GrantFiled: January 13, 1997Date of Patent: May 11, 1999Assignee: Packard Bell NEC, Inc.Inventors: James L. Walker, Michael D. Maddix, Steven L. Belt
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Patent number: 5901332Abstract: A data bus for connecting information processing devices is configurable into a plurality of subbusses in order to fully utilize the data bus capacity. The size and data transfer direction of each subbus, as well as the data transfer speed of each subbus, is independent of the other subbusses. Also, the data bus can be reconfigured to meet changing system requirements. A data bus controller is thus provided to accomplish this data bus reconfiguration. The reconfiguration may be accomplished in accordance with one of a plurality of information flow templates which may be stored in a memory. A method of configuring a data bus is also provided wherein information transfer needs of a system are identified and the data bus is configured according to the identified information transfer means. The reconfiguration in accordance with the information transfer needs may be accomplished in accordance with one or more information flow templates which may be stored in a memory.Type: GrantFiled: August 29, 1997Date of Patent: May 4, 1999Assignee: Advanced Micro Devices Inc.Inventors: Douglas D. Gephardt, Brett B. Stewart, Rita M. Wisor, Steven L. Belt, Drew J. Dutton
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Patent number: 5872942Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced multimedia bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.Type: GrantFiled: September 10, 1997Date of Patent: February 16, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Scott Swanstrom, Steven L. Belt
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Patent number: 5790815Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced multimedia bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.Type: GrantFiled: May 17, 1996Date of Patent: August 4, 1998Assignee: Advanced Micro Devices, Inc.Inventors: Scott Swanstrom, Steven L. Belt
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Patent number: 5765004Abstract: A laptop computer system includes a protected mode microprocessor capable of operating in restricted and unrestricted modes, and an arrangement which in response to a predetermined condition saves information from the processor and then forcibly switches the processor to its unrestricted mode of operation. When running a multi-tasking operating system where an application program is being executed in a restricted mode, a suspend/resume operation can be carried out in which the system is substantially powered down and then powered back up, and will resume the interrupted application with the restricted mode back in effect. Further, set-up changes such as adjustment of the processor speed can be made without exiting the application program running in the restricted mode.Type: GrantFiled: June 1, 1995Date of Patent: June 9, 1998Assignee: Vantus Technologies, Inc.Inventors: Mark J. Foster, Saifuddin T. Fakhruddin, James L. Walker, Matthew B. Mendelow, Jiming Sun, Rodman S. Brahman, Michael P. Krau, Brian D. Willoughby, Michael D. Maddix, Steven L. Belt, Scott A. Hovey, Mark A. Ruthenbeck
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Patent number: 5754190Abstract: A method and apparatus for transferring original data which includes images, between two stations located a distance apart, without actual transmission of the image portion of the data. A library of images are provided at each of the stations. The image to be transferred is processed into a description of the image which allows the reproduction of the image at the receiving end of the transmission using the images contained in the image library in the receiving station.Type: GrantFiled: June 7, 1995Date of Patent: May 19, 1998Assignee: Advanced Micro DevicesInventors: Drew J. Dutton, Douglas D. Gephardt, Steven L. Belt, Brett B. Stewart, Rita M. Wisor