Abstract: A cache storage system having hardware for in-cache execution of storage-storage and storage-immediate instructions thereby obviating the need for data to be moved from the cache to a separate execution unit and back to cache.

Abstract: A multiprocessor system includes a system of store queues and write buffers in a hierarchical first level and second level memory system including a first level store queue for storing instructions and/or data from a processor of the multiprocessor system prior to storage in a first level of cache, a second level store queue for storing the instructions and/or data from the first level store queue and a plurality of write buffers for storing the instructions and/or data from the second level store queue prior to storage in a second level of cache. The multiprocessor system includes hierarchical levels of caches, including a first level of cache associated with each processor, a single shared second level of cache shared by all the processors, and a third level of main memory connected to the shared second level cache. A first level store queue, associated with each processor, receives the data and/or instructions from its processor and stores the data and/or instructions in the first level of cache.

Abstract: A computer system having trace arrays and registers that provide error tracing that permits retry of operations in a pipelined, multiprocessing environment after the operations have been allowed to quiesce. The trace arrays in each retry domain include one master trace array. The master arrays store an event trace identification code, a cross reference event trace indentification code, an error flag, and a cross reference bit. The trace arrays provide a record of the events occurring between the occurrence of an error and the completion of quiescence, when retry can be attemped. Error registers are used to record events in which errors occur during quiescence, where trace arrays cannot be implemented.