Abstract: A method and computer program for detecting and locating defects in integrated circuit die from stimulation of statistical outlier signatures includes receiving as input a test value of an electrical parameter measured for each of a plurality of identically designed electrical circuits, identifying one of the identically designed electrical circuits as an outlier for which the test value of the electrical parameter varies from a mean test value of the electrical parameter for the plurality of identically designed electrical circuits by at least a selected difference, monitoring the test value while subjecting a location on the outlier to a stimulus to detect a change in the test value as a function of the location, and generating as output the location for which the change in the test value is detected to identify a defect in the outlier.

Abstract: A circuit for providing a bit string, the circuit including a plurality of commonly wired, substantially identical bit cells in a string, where each bit cell is designed to read as only one of a logical high and a logical low upon a given input, and each bit cell comprises a bit in the bit string. An enable line is associated with each of the bit cells, where each enable line has a fuse that is adapted to be activated upon application of a signal by a tester. Each bit cell is configured so as to be logically isolated from all others of the plurality of bit cells in the string when the fuse associated with the bit cell is activated. The circuit is adapted such that bit cells having fuses that are activated are logically removed from the bit string.

Abstract: A circuit for providing a bit string, the circuit including a plurality of commonly wired, substantially identical bit cells in a string, where each bit cell is designed to read as only one of a logical high and a logical low upon a given input, and each bit cell comprises a bit in the bit string. An enable line is associated with each of the bit cells, where each enable line has a fuse that is adapted to be activated upon application of a signal by a tester. Each bit cell is configured so as to be logically isolated from all others of the plurality of bit cells in the string when the fuse associated with the bit cell is activated. The circuit is adapted such that bit cells having fuses that are activated are logically removed from the bit string.

Abstract: A system is provided for yield enhancement in programmable logic. The system includes first and second random combinational logic, first and second sets of IP logic blocks, and first and second BIST/MUX controllers. The first controller is electrically connected between the first logic and each of the blocks in the first set and electrically connected between each of the blocks in the first set and the second logic. The second controller is connected in the same manner with respect to the second set of blocks. The controllers are configured to test the blocks for functionality or non-functionality, to identify functional ones of the blocks and to provide electrical connections between a predetermined number of the functional blocks and the first and second logic.

Abstract: A method and a means for determining an IDDQ test limit of an integrated circuit are provided. In particular, a method is provided which includes measuring the IDDQ value of a test structure formed upon a die derived from the same lot of wafers as an integrated circuit. The method may further include setting the IDDQ test limit based upon the measured IDDQ value. In some embodiments, setting the IDDQ test limit may include correlating the IDDQ value of the test structure to calibration data. Accordingly, a means for conducting such a method may include one or more test structures formed upon a die and calibration data adapted to correlate a test structure IDDQ value to an IDDQ test limit of an integrated circuit. In some cases, the means for determining the IDDQ test limit may further include a means for increasing a substrate leakage current of the test structure.

Abstract: A backside failure analysis capable integrated circuit package having a removable plug for exposing the backside of the die or a cavity on the backside of the package for exposing the backside of the die. The package uses either a standard lead frame which must be removed prior to conducting a backside failure analysis or a non-standard lead frame which provides for access to the back side of the die.

Abstract: A method of screening EEPROMs for data retention quality employs a UV source which is arranged to be impinged upon the devices while in wafer form, at or near an electrical probe station. Known data is stored in memory cells on an EEPROM chip while the chip is in wafer form, at a probe station. The wafer is then moved beneath a UV silo near the probe station and exposed to UV light, for a period of time and at an intensity which is sufficient to cause leakage of charge from potentially leaky floating gates. The wafer is again subjected to electrical probe where the amount of change in retained charge is detected. From this test, an indication of the charge retention ability of the devices is obtained. The UV light increases the energy state of the stored charge thus accelerating the decay of the stored charge located on the floating gates in the EEPROM device. Bits that have inherent leakage paths decay more rapidly.