Patents by Inventor Steven L. Kosier

Steven L. Kosier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Trench semiconductor device layout configurations
    Patent number: 11245006
    Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: February 8, 2022
    Assignees: Polar Semiconductor, LLC, SANKEN ELECTRIC CO., LTD.
    Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven L. Kosier, Peter West
  • TRENCH SEMICONDUCTOR DEVICE LAYOUT CONFIGURATIONS
    Publication number: 20200127092
    Abstract: A trench semiconductor device includes a layer of semiconductor material, an exterior trench pattern formed in the layer of semiconductor material, and an interior trench pattern formed in the layer of semiconductor material, at least partially surrounded by the exterior trench pattern. The exterior trench pattern includes a plurality of exterior trench portions that are each lined with dielectric material and filled with conductive material, and the interior trench pattern includes a plurality of interior trench portions that are each lined with dielectric material and filled with conductive material.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 23, 2020
    Applicants: Polar Semiconductor, LLC, SANKEN ELECTRIC CO., LTD.
    Inventors: Dosi Dosev, Don Rankila, Tatsuya Kamimura, Shunsuke Fukunaga, Steven L. Kosier, Peter West
  • Diode structure to suppress parasitic current
    Patent number: 7466004
    Abstract: A diode conducts current between an anode terminal and a cathode terminal. The diode includes a parasitic transistor formed between one of the terminals and the substrate. The diode also includes a second transistor that competes with the parasitic transistor to direct current flow between the anode terminal and the cathode terminal.
    Type: Grant
    Filed: June 19, 2006
    Date of Patent: December 16, 2008
    Assignee: Polar Semiconductor, Inc.
    Inventors: Steven L. Kosier, David M. Elwood
  • Diode structure to suppress parasitic current
    Publication number: 20070290289
    Abstract: A diode conducts current between an anode terminal and a cathode terminal. The diode includes a parasitic transistor formed between one of the terminals and the substrate. The diode also includes a second transistor that competes with the parasitic transistor to direct current flow between the anode terminal and the cathode terminal.
    Type: Application
    Filed: June 19, 2006
    Publication date: December 20, 2007
    Applicant: Polar Semiconductor, Inc.
    Inventors: Steven L. Kosier, David M. Elwood
  • Bipolar junction transistor antifuse
    Patent number: 7071533
    Abstract: An antifuse device is constructed from a bipolar junction transistor (BJT). The BJT includes a collector, a base, and an emitter. In one embodiment the BJT is formed inherently within a field effect transistor (FET), including a first doped region, a second doped region, a gate, and a body region. The collector of the BJT is realized by the first doped region of the FET, the emitter of the BJT is realized by the second doped region of the FET, and the base of the BJT is realized by the body region. A high resistance path exists between the collector and the base. A first input voltage is connected to the collector and a second input voltage is connected to the base. A switch connects the emitter to a fixed potential when the switch is closed.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: July 4, 2006
    Assignee: Polar Semiconductor, Inc.
    Inventors: Kurt N. Kimber, David D. Litfin, Joseph Burkhardt, Steven L. Kosier
  • System and method for defining a semiconductor device layout
    Patent number: 6804809
    Abstract: A method to create a layout of a semiconductor device for the purpose of fabricating the semiconductor device involves first providing a plurality of partial-area layout cells and then generating the layout of the semiconductor device by placing the plurality of the partial-area layout cells together. The layout can be conveniently expanded to a desirable size by replicating or repeating certain repeatable cells.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: October 12, 2004
    Assignee: PolarFab, LLC
    Inventors: Peter West, Ronald Harlan, Steven L. Kosier