Patents by Inventor Steven L. Merchant
Steven L. Merchant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8274131Abstract: A semiconductor device comprising a first transistor device (130) on or in a semiconductor substrate (115) and a second transistor device (132) on or in the substrate. The device further comprises an insulating trench (200) located between the first transistor device and the second transistor device. At least one upper corner (610) of the insulating trench is a rounded corner in a lateral plane (620) of the substrate.Type: GrantFiled: December 7, 2010Date of Patent: September 25, 2012Assignee: Texas Instruments IncorporatedInventors: Sameer P. Pendharkar, John Lin, Philip L. Hower, Steven L. Merchant
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Publication number: 20110073955Abstract: A semiconductor device comprising a first transistor device (130) on or in a semiconductor substrate (115) and a second transistor device (132) on or in the substrate. The device further comprises an insulating trench (200) located between the first transistor device and the second transistor device. At least one upper corner (610) of the insulating trench is a rounded corner in a lateral plane (620) of the substrate.Type: ApplicationFiled: December 7, 2010Publication date: March 31, 2011Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Sameer P. Pendharkar, John Lin, Philip L. Hower, Steven L. Merchant
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Patent number: 7910417Abstract: A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.Type: GrantFiled: July 21, 2008Date of Patent: March 22, 2011Assignee: Texas Instruments IncorporatedInventors: Philip L. Hower, David A. Walch, John Lin, Steven L. Merchant
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Patent number: 7846789Abstract: A semiconductor device comprising a first transistor device on or in a semiconductor substrate and a second transistor device on or in the substrate. The device further comprises an insulating trench located between the first transistor device and the second transistor device. At least one upper corner of the insulating trench is a rounded corner in a lateral plane of the substrate.Type: GrantFiled: October 16, 2007Date of Patent: December 7, 2010Assignee: Texas Instruments IncorporatedInventors: Sameer P. Pendharkar, John Lin, Philip L. Hower, Steven L. Merchant
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Patent number: 7736961Abstract: A high voltage field effect transistor device is fabricated. A substrate is provided. Isolation structures and well regions are formed therein. Drain well regions are formed within the well regions. An n-type channel stop resist mask is formed. N-type channel stop regions and n-type surface channel regions are formed. A p-type channel stop resist mask is formed. P-type channel stop regions and p-type surface channel regions are then formed. A dielectric layer is formed over the surface channel regions. Source regions are formed within the well regions. Drain regions are formed within the drain well regions. Back gate regions are formed within the well regions. Top gates are formed on the dielectric layer overlying the surface channel regions.Type: GrantFiled: June 28, 2005Date of Patent: June 15, 2010Assignee: Texas Instruments IncorporatedInventors: Steven L. Merchant, Philip L. Hower, Scott Paiva
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Patent number: 7605412Abstract: A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.Type: GrantFiled: September 22, 2006Date of Patent: October 20, 2009Assignee: Texas Instruments IncorporatedInventors: Philip L. Hower, David A. Walch, John Lin, Steven L. Merchant
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Publication number: 20090096033Abstract: A semiconductor device comprising a first transistor device on or in a semiconductor substrate and a second transistor device on or in the substrate. The device further comprises an insulating trench located between the first transistor device and the second transistor device. At least one upper corner of the insulating trench is a rounded corner in a lateral plane of the substrate.Type: ApplicationFiled: October 16, 2007Publication date: April 16, 2009Applicant: Texas Instruments IncorporatedInventors: Sameer P. Pendharkar, John Lin, Philip Hower, Steven L. Merchant
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Publication number: 20080299716Abstract: A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.Type: ApplicationFiled: July 21, 2008Publication date: December 4, 2008Inventors: Philip L. Hower, David A. Walch, John Lin, Steven L. Merchant
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Patent number: 7417270Abstract: A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.Type: GrantFiled: June 23, 2004Date of Patent: August 26, 2008Assignee: Texas Instruments IncorporatedInventors: Philip L. Hower, David A. Walch, John Lin, Steven L. Merchant
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Patent number: 7187034Abstract: Segmented power transistors and fabrication methods are disclosed in which transistor segments are spaced from one another to facilitate thermal diffusion, and in which other electrical devices can be formed in the spaces between transistor segments.Type: GrantFiled: July 9, 2004Date of Patent: March 6, 2007Assignee: Texas Instruments IncorporatedInventors: Philip L. Hower, John Lin, Sameer P. Pendharkar, Steven L. Merchant
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Publication number: 20040256669Abstract: Segmented power transistors and fabrication methods are disclosed in which transistor segments are spaced from one another to facilitate thermal diffusion, and in which other electrical devices can be formed in the spaces between transistor segments.Type: ApplicationFiled: July 9, 2004Publication date: December 23, 2004Inventors: Philip L. Hower, John Lin, Sameer P. Pendharkar, Steven L. Merchant
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Publication number: 20040222485Abstract: A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post.Type: ApplicationFiled: June 4, 2004Publication date: November 11, 2004Inventors: Sheldon D. Haynie, Steven L. Merchant, Sameer P. Pendharkar, Vladimir Bolkhovsky
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Patent number: 6815276Abstract: Segmented power transistors and fabrication methods are disclosed in which transistor segments are spaced from one another to facilitate thermal diffusion, and in which other electrical devices can be formed in the spaces between transistor segments.Type: GrantFiled: October 3, 2002Date of Patent: November 9, 2004Assignee: Texas Instruments IncorporatedInventors: Philip L. Hower, John Lin, Sameer P. Pendharkar, Steven L. Merchant
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Patent number: 6800917Abstract: A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post.Type: GrantFiled: December 17, 2002Date of Patent: October 5, 2004Assignee: Texas Instruments IncorporatedInventors: Sheldon D. Haynie, Steven L. Merchant, Sameer P. Pendharkar, Vladimir Bolkhovsky
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Patent number: 6797547Abstract: A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post.Type: GrantFiled: October 3, 2003Date of Patent: September 28, 2004Assignee: Texas Instruments IncorporatedInventors: Sheldon D. Haynie, Steven L. Merchant, Sameer P. Pendharkar, Vladimir Bolkhovsky
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Publication number: 20040129976Abstract: A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post.Type: ApplicationFiled: October 3, 2003Publication date: July 8, 2004Inventors: Sheldon D. Haynie, Steven L. Merchant, Sameer P. Pendharkar, Vladimir Bolkhovsky
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Publication number: 20040113223Abstract: A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post.Type: ApplicationFiled: December 17, 2002Publication date: June 17, 2004Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Sheldon D. Haynie, Steven L. Merchant, Sameer P. Pendharkar, Vladimir Bolkhovsky
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Publication number: 20040067617Abstract: Segmented power transistors and fabrication methods are disclosed in which transistor segments are spaced from one another to facilitate thermal diffusion, and in which other electrical devices can be formed in the spaces between transistor segments.Type: ApplicationFiled: October 3, 2002Publication date: April 8, 2004Inventors: Philip L. Hower, John Lin, Sameer P. Pendharkar, Steven L. Merchant
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Patent number: 6700160Abstract: An improved DMOS power transistor (20) with a single p-body implant (12) and including an n-type channel compensating implant (NCCI) (24). The improved DMOS power transistor (20) provides a more favorable trade-off between threshold voltage (VT) and on-state resistance, while increasing the safe operating area (SOA). The NCCI (24) also improves the off-state breakdown voltage, and allows a larger fraction of the gate bias voltage to be supported on the thin gate oxide (32). The present invention can be fabricated using self-aligned fabrication techniques so that the channel length (22) is insensitive to lithography equipment.Type: GrantFiled: October 17, 2000Date of Patent: March 2, 2004Assignee: Texas Instruments IncorporatedInventor: Steven L. Merchant
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Patent number: 6603157Abstract: A field effect transistor (30) has an array of transistors (31) made up of bonding pads (45-47) and sub-arrays of transistors (41-43). The bonding pads (45-47) are distributed between the sub-arrays of transistors (41-43) to reduce the maximum temperature that any portion of the FET (30) is exposed to while the FET (30) is in a conducting state. A similar effect can be appreciated by adjusting the threshold voltage or pinch-off resistance of the transistors in a portion (101) of an array of transistors (95).Type: GrantFiled: November 2, 2001Date of Patent: August 5, 2003Assignee: Motorola, Inc.Inventors: Phillipe Dupuy, Steven L. Merchant, Robert W. Baird