Patents by Inventor Steven L. Pollock

Steven L. Pollock has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6781573
    Abstract: An ergonomic mouse is designed to maximize productivity by reducing user fatigue and discomfort. The ergonomic mouse of the present invention includes a housing having a grippable portion that permits a user to grip the mouse substantially under its palm when the mouse rests on a flat surface such as a mouse pad. A concave portion in the housing receives the user's fingers. At least one button is positioned in the concave portion of the housing. The at least one button is actuated by a substantially horizontal force produced by a substantially horizontal motion of the tips of the fingers as the fingers curl in toward the palm.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: August 24, 2004
    Assignee: Intel Corporation
    Inventors: Ted T. Honma, Steven L. Pollock
  • Patent number: 6720956
    Abstract: An apparatus is provided that includes a touch-sensitive three-dimensional globe and an information handling system coupled to the touch-sensitive three-dimensional globe and adapted to receive the signals corresponding to the touched area of the globe. The information handling system may include a display device to display information regarding the area. A data accessing system may be coupled to the information handling system and be adapted to receive signals from the information handling system and transmit information from a data storage unit to the information handling system.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: April 13, 2004
    Assignee: Intel Corporation
    Inventors: Ted T. Honma, Steven L. Pollock
  • Patent number: 6707145
    Abstract: An apparatus, comprising a substrate having a surface, comprising an array of electrical contacts, and a plurality of electrical planes, where the plurality of electrical planes are positioned within the electrical contact array.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: March 16, 2004
    Assignee: Intel Corporation
    Inventors: Steven L. Pollock, Robert L. Olivier
  • Patent number: 6691242
    Abstract: The present invention is designed to test whether a Central Processing Unit (CPU) in a computer system is being overclocked. That is, being run at a speed higher than its rated or assigned speed. An important feature of the present invention is that it is internal to the computer system on which it operates. That is, the test of the present invention is implemented in the computer system's Basic Input/Output System or as microcode stored directly on the CPU. The end user need not resort to any external means such as a floppy or CD disk to test the CPU included in his/her computer system. If the CPU is not overclocked, the test runs invisible to the end user. If, on the other hand, the CPU is overclocked, the test allows the user to either continue with the normal boot up process or exit the boot up process to adjust the running speed to substantially match the assigned speed of the CPU.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: February 10, 2004
    Assignee: Intel Corporation
    Inventors: Steven L. Pollock, Ted T. Honma
  • Patent number: 6479886
    Abstract: An improved packaged IC is disclosed, which includes a semiconductor die mounted to a substrate and an EMI shield that encapsulates the semiconductor die. In addition, a ground pin is electrically coupled to the semiconductor die, a ferrite bead is electrically coupled to the EMI shield and the ground pin, and a package body encapsulates the EMI shield.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: November 12, 2002
    Assignee: Intel Corporation
    Inventors: Steven L. Pollock, Robert L. Olivier
  • Publication number: 20020084533
    Abstract: An apparatus, comprising a substrate having a surface, comprising an array of electrical contacts, and a plurality of electrical planes, where the plurality of electrical planes are positioned within the electrical contact array.
    Type: Application
    Filed: December 29, 2000
    Publication date: July 4, 2002
    Inventors: Steven L. Pollock, Robert L. Olivier
  • Patent number: 6392887
    Abstract: An electronic assembly that may include an elastomeric connector. The elastomeric connector may couple the solder ball of a BGA integrated circuit package to a substrate. The elastomeric connector provides an interconnect that may compensate for variations in the solder balls and a lack of flatness in the package and/or substrate.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: May 21, 2002
    Assignee: Intel Corporation
    Inventors: Jeffrey W. Day, Steven L. Pollock
  • Patent number: 6365960
    Abstract: An improved packaged IC is disclosed, which includes a semiconductor die mounted to a substrate and an EMI shield that encapsulates the semiconductor die. In addition, a package body encapsulates the EMI shield.
    Type: Grant
    Filed: June 19, 2000
    Date of Patent: April 2, 2002
    Assignee: Intel Corporation
    Inventors: Steven L. Pollock, Robert L. Olivier
  • Patent number: 6056601
    Abstract: A connector for mounting a processor card on a motherboard includes a base and an upper support chassis. The base is electrically and structurally coupled to a motherboard and the upper support chassis is mounted on the base. A processor card is received within the upper support chassis for mounting of the card to the motherboard. When the card is received within the upper support chassis, the processor card is positioned substantially parallel to the motherboard.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: May 2, 2000
    Assignee: Intel Corporation
    Inventors: Steven L. Pollock, Robert Olivier