Patents by Inventor Steven L. Scott
Steven L. Scott has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240056385Abstract: A switch architecture for a data-driven intelligent networking system is provided. The system can accommodate dynamic traffic with fast, effective congestion control. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow are acknowledged after reaching the egress point of the network, and the acknowledgement packets are sent back to the ingress point of the flow along the same data path. As a result, each switch can obtain state information of each flow and perform flow control on a per-flow basis.Type: ApplicationFiled: October 23, 2023Publication date: February 15, 2024Inventors: Abdulla M. Bataineh, Jonathan Paul Beecroft, Thomas L. Court, Anthony M. Ford, Edwin L. Froese, David Charles Hewson, Joseph Kopnick, Andrew Kopser, Duncan Roweth, Gregory Faanes, Michael Higgins, Timothy J. Johnson, Trevor Jones, James Reinhard, Edward J. Turner, Steven L. Scott
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Patent number: 11818037Abstract: A switch architecture for a data-driven intelligent networking system is provided. The system can accommodate dynamic traffic with fast, effective congestion control. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow are acknowledged after reaching the egress point of the network, and the acknowledgement packets are sent back to the ingress point of the flow along the same data path. As a result, each switch can obtain state information of each flow and perform flow control on a per-flow basis.Type: GrantFiled: March 23, 2020Date of Patent: November 14, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Abdulla M. Bataineh, Jonathan P. Beecroft, Thomas L. Court, Anthony M. Ford, Edwin L. Froese, David Charles Hewson, Joseph G. Kopnick, Andrew S. Kopser, Duncan Roweth, Gregory Faanes, Michael Higgins, Timothy J. Johnson, Trevor Jones, James Reinhard, Edward J. Turner, Steven L. Scott, Robert L. Alverson
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Publication number: 20220210094Abstract: A switch architecture for a data-driven intelligent networking system is provided. The system can accommodate dynamic traffic with fast, effective congestion control. The system can maintain state information of individual packet flows, which can be set up or released dynamically based on injected data. Each flow can be provided with a flow-specific input queue upon arriving at a switch. Packets of a respective flow are acknowledged after reaching the egress point of the network, and the acknowledgement packets are sent back to the ingress point of the flow along the same data path. As a result, each switch can obtain state information of each flow and perform flow control on a per-flow basis.Type: ApplicationFiled: March 23, 2020Publication date: June 30, 2022Inventors: Abdulla M. Bataineh, Jonathan P. Beecroft, Thomas L. Court, Anthony M. Ford, Edwin L. Froese, David Charles Hewson, Joseph G. Kopnick, Andrew S. Kopser, Duncan Roweth, Gregory Faanes, Michael Higgins, Timothy J. Johnson, Trevor Jones, James Reinhard, Edward J. Turner, Steven L. Scott, Robert L. Alverson
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Patent number: 10860524Abstract: A multiprocessor computer system comprises a first node operable to access memory local to a remote node by receiving a virtual memory address from a requesting entity in node logic in the first node. The first node creates a network address from the virtual address received in the node logic, where the network address is in a larger address space than the virtual memory address, and sends a fast memory access request from the first node to a network node identified in the network address.Type: GrantFiled: May 27, 2015Date of Patent: December 8, 2020Assignee: Intel CorporationInventors: Dennis C. Abts, Robert Alverson, Edwin Froese, Howard Pritchard, Steven L. Scott
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Patent number: 10153985Abstract: A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes, a plurality of routers, each router directly coupled to a plurality of terminal nodes, the routers coupled to one another and arranged into a group, and a plurality of groups of routers, such that each group is connected to each other group via at least one direct connection.Type: GrantFiled: February 17, 2017Date of Patent: December 11, 2018Assignees: Intel Corporation, The Board of Trustees of the Leland Stanford Junior UniversityInventors: John Kim, Dennis C. Abts, Steven L. Scott, William J. Dally
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Publication number: 20170353401Abstract: A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes, a plurality of routers, each router directly coupled to a plurality of terminal nodes, the routers coupled to one another and arranged into a group, and a plurality of groups of routers, such that each group is connected to each other group via at least one direct connection.Type: ApplicationFiled: February 17, 2017Publication date: December 7, 2017Applicants: Intel Corporation, The Board of Trustees of the Leland Stanford Junior UniversityInventors: John Kim, Dennis C. Abts, Steven L. Scott, William J. Dally
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Patent number: 9614786Abstract: A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes, a plurality of routers, each router directly coupled to a plurality of terminal nodes, the routers coupled to one another and arranged into a group, and a plurality of groups of routers, such that each group is connected to each other group via at least one direct connection.Type: GrantFiled: December 27, 2014Date of Patent: April 4, 2017Assignees: Intel Corporation, The Board of Trustees of the Leland Stanford Junior UniversityInventors: John Kim, Dennis C. Abts, Steven L. Scott, William J. Dally
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Patent number: 9537772Abstract: A system and method for routing in a high-radix network. A packet is received and examined to determine if the packet can be routed adaptively. If the packet can be routed adaptively, the packet is routed adaptively, wherein routing adaptively includes selecting a column, computing a column mask, routing the packet to the column; and selecting an output port as a function of the column mask. If the packet can be routed deterministically, routing deterministically, wherein routing deterministically includes accessing a routing table to obtain an output port and routing the packet to the output port from the routing table.Type: GrantFiled: June 20, 2014Date of Patent: January 3, 2017Assignee: Intel CorporationInventors: Steven L. Scott, Gregory Hubbard, Dennis C. Abts
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Patent number: 9294551Abstract: A data-processing system and method for performing collective operations. Some embodiments provide a plurality of leaf software processes, a plurality of collective engines (CEs), and a network operatively coupled to the plurality of CEs, wherein collective operations messages are sent between CEs. Each of the plurality of hierarchies includes a root, leaf CEs, and one or more intermediate levels of CEs between the root and the leaf CEs. Each CE except the root is configured to have a parent CE, and each non-leaf CE in the hierarchy that is not the root CE and not one of the leaf CEs has one or more child CEs. Data is sent from software processes to one or more of the plurality of CEs, and data is received to one or more software processes from one or more of the plurality of collective engines. The root CE outputs a final result.Type: GrantFiled: March 13, 2013Date of Patent: March 22, 2016Assignee: Cray Inc.Inventors: Edwin L. Froese, Robert Baird, Steven L. Scott
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Publication number: 20150378961Abstract: A multiprocessor computer system comprises a first node operable to access memory local to a remote node by receiving a virtual memory address from a requesting entity in node logic in the first node. The first node creates a network address from the virtual address received in the node logic, where the network address is in a larger address space than the virtual memory address, and sends a fast memory access request from the first node to a network node identified in the network address.Type: ApplicationFiled: May 27, 2015Publication date: December 31, 2015Applicant: Intel CorporationInventors: Dennis C. Abts, Robert Alverson, Edwin Froese, Howard Pritchard, Steven L. Scott
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Patent number: 9201689Abstract: A method and system for software emulation of hardware support for multi-threaded processing using virtual hardware threads is provided. A software threading system executes on a node that has one or more processors, each with one or more hardware threads. The node has access to local memory and access to remote memory. The software threading system manages the execution of tasks of a user program. The software threading system switches between the virtual hardware threads representing the tasks as the tasks issue remote memory access requests while in user privilege mode. Thus, the software threading system emulates more hardware threads than the underlying hardware supports and switches the virtual hardware threads without the overhead of a context switch to the operating system or change in privilege mode.Type: GrantFiled: April 22, 2011Date of Patent: December 1, 2015Assignee: Cray Inc.Inventors: Steven L. Scott, Gregory B. Titus, Sung-Eun Choi, Troy A. Johnson, David Mizell, Michael F. Ringenburg, Karlon West
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Publication number: 20150186318Abstract: A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes, a plurality of routers, each router directly coupled to a plurality of terminal nodes, the routers coupled to one another and arranged into a group, and a plurality of groups of routers, such that each group is connected to each other group via at least one direct connection.Type: ApplicationFiled: December 27, 2014Publication date: July 2, 2015Inventors: John Kim, Dennis C. Abts, Steven L. Scott, William J. Dally
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Patent number: 9069672Abstract: A multiprocessor computer system comprises a first node operable to access memory local to a remote node by receiving a virtual memory address from a requesting entity in node logic in the first node. The first node creates a network address from the virtual address received in the node logic, where the network address is in a larger address space than the virtual memory address, and sends a fast memory access request from the first node to a network node identified in the network address.Type: GrantFiled: June 12, 2009Date of Patent: June 30, 2015Assignee: Intel CorporationInventors: Dennis C. Abts, Robert Alverson, Edwin Froese, Howard Pritchard, Steven L. Scott
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Publication number: 20140301390Abstract: A system and method for routing in a high-radix network. A packet is received and examined to determine if the packet can be routed adaptively. If the packet can be routed adaptively, the packet is routed adaptively, wherein routing adaptively includes selecting a column, computing a column mask, routing the packet to the column; and selecting an output port as a function of the column mask. If the packet can be routed deterministically, routing deterministically, wherein routing deterministically includes accessing a routing table to obtain an output port and routing the packet to the output port from the routing table.Type: ApplicationFiled: June 20, 2014Publication date: October 9, 2014Inventors: Steven L. Scott, Gregory Hubbard, Dennis C. Abts
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Patent number: 8792512Abstract: A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, to maintain a message buffer entry in the sender comprising the sent packets, to track acknowledgment from the receiver that sent packets have been received; to maintain a timer indicating the time since message data has been sent, and to resend packets not acknowledged upon the timer reaching a timeout state. The receiving processor node is operable to send acknowledgement to the sender that received packets have been received, to track packets using a received message table to track which packets comprising part of the message have been received and whether all packets in the message have been received, and to process packets once all packets in a message are received to reassemble the received message.Type: GrantFiled: June 7, 2007Date of Patent: July 29, 2014Assignee: Intel CorporationInventors: Steven L. Scott, Dennis C. Abts, Robert Alverson, Edwin Froese
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Patent number: 8774203Abstract: A multiprocessor computer system comprises a sending processor node and a receiving processor node. The sending processor node is operable to send packets comprising part of a message to a receiver, and to send a message complete packet after all packets in the message are sent. The message complete packet includes an indicator of the number of packets in the message, and the message is recognized as complete in the receiver once the number of packets indicated in the message complete packet have been received for the message. The sender tracks acknowledgment from the receiver of receipt of the sent packets; and notifies the receiver when it has received all packets comprising a part of the message.Type: GrantFiled: June 7, 2007Date of Patent: July 8, 2014Assignee: Intel CorporationInventors: Steven L. Scott, Dennis C. Abts, Robert Alverson, Edwin Froese
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Patent number: 8761166Abstract: A system and method for routing in a high-radix network. A packet is received and examined to determine if the packet can be routed adaptively. If the packet can be routed adaptively, the packet is routed adaptively, wherein routing adaptively includes selecting a column, computing a column mask, routing the packet to the column; and selecting an output port as a function of the column mask. If the packet can be routed deterministically, routing deterministically, wherein routing deterministically includes accessing a routing table to obtain an output port and routing the packet to the output port from the routing table.Type: GrantFiled: November 9, 2010Date of Patent: June 24, 2014Assignee: Intel CorporationInventors: Steven L. Scott, Gregory Hubbard, Dennis C. Abts
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Patent number: 8601236Abstract: A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core.Type: GrantFiled: February 29, 2012Date of Patent: December 3, 2013Assignee: Cray Inc.Inventors: Gregory J. Faanes, Eric P. Lundberg, Abdulla Bataineh, Timothy J. Johnson, Michael Parker, James Robert Kohn, Steven L. Scott, Robert Alverson
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Patent number: 8386750Abstract: A multiprocessor computer system has a plurality of first processors having a first addressable memory space, and a plurality of second processors having a second addressable memory space. The second addressable memory space is of a different size than the first addressable memory space, and the first addressable memory space and second addressable memory space comprise a part of the same common address space.Type: GrantFiled: October 31, 2008Date of Patent: February 26, 2013Assignee: Cray Inc.Inventors: Michael Parker, Timothy J. Johnson, Laurence S. Kaplan, Steven L. Scott, Robert Alverson, Skef Iterum
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Patent number: 8380935Abstract: An atomic memory operation cache comprises a cache memory operable to cache atomic memory operation data, a write timer, and a cache controller. The cache controller is operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon expiration of the write timer, and is further operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon eviction of the one or more dirty atomic memory operation cache entries from the cache memory.Type: GrantFiled: June 12, 2009Date of Patent: February 19, 2013Assignee: Cray Inc.Inventors: Dennis C. Abts, Steven L. Scott