Abstract: An engine starting cycle cranking and rest period timing circuit and an overcrank shut down circuit includes a 24 stage frequency divider connected to starting motor relays, and an engine starter disconnect circuit and a start signal circuit functioning to provide a predetermined number of engine starter motor cranking periods followed by rest periods. The frequency divider circuit is connected to provide coordination of the starter motor cranking cycle with an overcrank signal generated by the frequency divider. An overcrank signal will activate only when all three output terminals of the frequency divider circuit are simultaneously of the same signal amplitude which will always occur at the predetermined maximum number of crank periods.