Abstract: Component access control includes: receiving, by an access control module, permissions specifying authorization of physical access to one or more secured components of a computing system by one or more requestors; receiving, by the access control module from a requestor, a request to physically access one of the secured components of the computing system; determining, by the access control module based on the permissions, whether the requestor is authorized to physically access the secured component; and responsive to determining that the requestor is authorized to physically access the secured component, granting the requestor physical access to the secured component while prohibiting the requestor from physically accessing other secured components of the computing system.

Abstract: Aspects of the present invention disclose a DIMM extraction tool for extracting a DIMM from a DIMM socket. Exemplary embodiments of the DIMM extraction tool include a frame adapted for use as an air baffle within the DIMM socket, a first arm and a second arm pivotably connected to the frame. When the first arm and second arm are in a resting position, the first and second arm respectively engage a first resting detent and a second resting detent to prevent pivotable rotation of the first arm and second arm in exemplary embodiments of the DIMM extraction tool. When the first arm and second arm are in a working position, the first arm and second arm respectively are adapted to releasably engage the DIMM and bias resilient latching arm of the DIMM socket.

Abstract: Controlling a plurality of serial peripheral interface (‘SPI’) peripherals using a single chip select in a computing system, the computing system including an SPI master, a first SPI peripheral, and a second SPI peripheral, wherein the first SPI peripheral is operatively coupled to the second SPI peripheral, including: receiving, by the first SPI peripheral, a signal from the SPI master; determining, by the first SPI peripheral, whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral; responsive to determining that the first SPI peripheral is the backup SPI peripheral, transmitting, by the first SPI peripheral to the second SPI peripheral, the signal; and responsive to determining that the first SPI peripheral is the primary SPI peripheral: servicing, by the first SPI peripheral, an instruction contained in the signal; and transmitting, by the first SPI peripheral to the second SPI peripheral, a response signal.

Abstract: A system, method, and/or computer program product comprises an input/output (I/O) bus and an intelligent current bank that couples a voltage source to the I/O bus. The intelligent current bank includes an ammeter that measures a real-time flow of current to the I/O bus. In response to the current to the I/O bus exceeding a predetermined level, an intelligent Pulse-Width Modulator (iPWM) within the intelligent current bank selectively decreases current to one or more electronic devices on the I/O bus by shortening a duty cycle of voltage being received by the iPWM from the voltage source.

Abstract: A system, method, and/or computer program product comprises an input/output (I/O) bus and an intelligent current bank that couples a voltage source to the I/O bus. The intelligent current bank includes an ammeter that measures a real-time flow of current to the I/O bus. In response to the current to the I/O bus exceeding a predetermined level, an intelligent Pulse-Width Modulator (iPWM) within the intelligent current bank selectively decreases current to one or more electronic devices on the I/O bus by shortening a duty cycle of voltage being received by the iPWM from the voltage source.

Abstract: A hardware system comprises a master device and a slave device that are coupled by a signal line. A frequency generator in the master device places a selected frequency signal on the signal line. A frequency detector/comparator in the slave device, which is coupled to the signal line, determines whether the selected frequency signal on the signal line matches a predetermined frequency for the slave device. If the selected frequency signal matches the predetermined frequency, then a chip select node on the slave device is enabled, in order to permit a data exchange session between the master device and the slave device.

Abstract: In accordance with one embodiment of the invention, an I2C bus multiplexing circuit for use in an I2C bus interface can be provided. The I2C bus multiplexing circuit can facilitate multiplexer switching in an I2C bus interface by detecting a start command from an I2C master device via an I2C bus, buffering data from the I2C master device, detecting a clock frequency of a bus serial clock (SCL) line of the I2C master device, holding the serial data (SDA) line of the I2C master device in a clock stretch state and selecting a port based on the detected clock frequency of the SCL of the I2C master device. The method further can include sending the buffered data to an I2C slave device on the selected port. The method further can include receiving an acknowledgement from the I2C slave device on the selected port.

Abstract: A serial peripheral interface (SPI) system including a bus adapter is disclosed. The bus adapter may include a data converter that may be adapted to receive respective first and second data from a first master output peripheral input (MOPI) line and a chip select line from a SPI master device. The data converter may also be adapted to interleave the first and second data, and the data converter may be adapted to transmit the interleaved first and second data synchronously with a second clock signal on a second MOPI line. The bus adapter may also include a clock rate adjuster adapted to generate the second clock signal to transmit to a SPI peripheral device. The second clock signal may be adapted to enable the SPI peripheral device to read the transmitted data.

Abstract: A system, method, and/or computer program product comprises an input/output (I/O) bus and an intelligent current bank that couples a voltage source to the I/O bus. The intelligent current bank includes an ammeter that measures a real-time flow of current to the I/O bus. In response to the current to the I/O bus exceeding a predetermined level, an intelligent Pulse-Width Modulator (iPWM) within the intelligent current bank selectively decreases current to one or more electronic devices on the I/O bus by shortening a duty cycle of voltage being received by the iPWM from the voltage source.

Abstract: Methods, apparatuses, and computer program products for dynamically reconfiguring a primary processor identity within a multi-processor socket server are provided. Embodiments include detecting, by the service processor, a processor socket reconfiguration event corresponding to a first processor socket; disabling, by the service processor, the first processor socket of the server in response to detecting the processor socket reconfiguration event; and reassigning, by the service processor, the primary processor identity to a second processor socket of the server.

Abstract: A serial peripheral interface (SPI) system including a bus adapter is disclosed. The bus adapter may include a data converter that may be adapted to receive respective first and second data from a first master output peripheral input (MOPI) line and a chip select line from a SPI master device. The data converter may also be adapted to interleave the first and second data, and the data converter may be adapted to transmit the interleaved first and second data synchronously with a second clock signal on a second MOPI line. The bus adapter may also include a clock rate adjuster adapted to generate the second clock signal to transmit to a SPI peripheral device. The second clock signal may be adapted to enable the SPI peripheral device to read the transmitted data.

Abstract: Controlling a plurality of serial peripheral interface (‘SPI’) peripherals using a single chip select in a computing system, the computing system including an SPI master, a first SPI peripheral, and a second SPI peripheral, wherein the first SPI peripheral is operatively coupled to the second SPI peripheral, including: receiving, by the first SPI peripheral, a signal from the SPI master; determining, by the first SPI peripheral, whether the first SPI peripheral is a primary SPI peripheral or a backup SPI peripheral; responsive to determining that the first SPI peripheral is the backup SPI peripheral, transmitting, by the first SPI peripheral to the second SPI peripheral, the signal; and responsive to determining that the first SPI peripheral is the primary SPI peripheral: servicing, by the first SPI peripheral, an instruction contained in the signal; and transmitting, by the first SPI peripheral to the second SPI peripheral, a response signal.

Abstract: In accordance with one embodiment of the invention, an I2C bus multiplexing circuit for use in an I2C bus interface can be provided. The I2C bus multiplexing circuit can facilitate multiplexer switching in an I2C bus interface by detecting a start command from an I2C master device via an I2C bus, buffering data from the I2C master device, detecting a clock frequency of a bus serial clock (SCL) line of the I2C master device, holding the serial data (SDA) line of the I2C master device in a clock stretch state and selecting a port based on the detected clock frequency of the SCL of the I2C master device. The method further can include sending the buffered data to an I2C slave device on the selected port. The method further can include receiving an acknowledgement from the I2C slave device on the selected port.

Abstract: A hardware system comprises a master device and a slave device that are coupled by a signal line. A frequency generator in the master device places a selected frequency signal on the signal line. A frequency detector/comparator in the slave device, which is coupled to the signal line, determines whether the selected frequency signal on the signal line matches a predetermined frequency for the slave device. If the selected frequency signal matches the predetermined frequency, then a chip select node on the slave device is enabled, in order to permit a data exchange session between the master device and the slave device.

Abstract: Methods, apparatuses, and computer program products for dynamically reconfiguring a primary processor identity within a multi-processor socket server are provided. Embodiments include detecting, by the service processor, a processor socket reconfiguration event corresponding to a first processor socket; disabling, by the service processor, the first processor socket of the server in response to detecting the processor socket reconfiguration event; and reassigning, by the service processor, the primary processor identity to a second processor socket of the server.

Abstract: Methods, apparatus, and products are disclosed for dynamically configuring overcurrent protection in a power supply for components of an electrically powered system, including summing by a master service processor, during powered operation of the system, the present power requirements of components presently installed in the system and setting by the master service processor an overcurrent trip point of the power supply in dependence upon the sum of the present power requirements of the components.

Abstract: Methods, apparatus, and products are disclosed for dynamically configuring overcurrent protection in a power supply for components of an electrically powered system, including summing by a master service processor, during powered operation of the system, the present power requirements of components presently installed in the system and setting by the master service processor an overcurrent trip point of the power supply in dependence upon the sum of the present power requirements of the components.

Abstract: A self-configuring memory subsystem for a computer system allows the insertion of memory modules into any of the available expansion sockets without the need for setting switches or inserting the modules in a predefined or restricted sequence and without the requirement of additional logic circuitry or microcode in the computer. Each of the memory modules utilized with the subsystem has a number of size identification bits, each bit being connected to a known value, such as ground or left floating. The size bits are detected by logic circuitry embodied in a programmable logic device (PLD) so that the total memory space may be properly mapped. The PLD is programmed so that it uses the identification bits to "map" the installed memory modules into the logical memory address space as accessed by the memory controller so that each memory location of the memory modules has an allocated memory location without addressing ambiguities.