Patents by Inventor Steven L. White
Steven L. White has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8191175Abstract: A visor protector for caps having a visor including a periphery having a front edge, a pair of lateral edges, and upper and lower sides. The visor protector includes a flexible body having an upper portion and a lower portion. The upper portion of the flexible body meets the lower portion of the flexible body at a leading edge of the flexible body. The upper portion of the flexible body is receivable on the upper side of the visor, and the lower portion of the flexible body is receivable on the lower side of the visor. The upper and lower portions of the flexible body cooperate to define a substantial U-shape, wherein the visor is receivable between the upper and lower portions such that the leading edge of the flexible body is substantially aligned with the front edge of the visor. The visor protector includes a pair of spring clips that each have a first leg that is engageable with the upper portion of the flexible body and a second leg that is engageable with the lower portion of the flexible body.Type: GrantFiled: July 17, 2009Date of Patent: June 5, 2012Inventor: Steven L. White
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Patent number: 7266161Abstract: An apparatus and method provides efficient parallel processing for use with a single-bit sampler that provides single-bit samples at a high sample rate. A serial-to-parallel converter converts the single-bit samples into parallel single-bit samples at a reduced sample rate. A digital quadrature mix performs a frequency shift to the parallel single-bit samples and simultaneously performs a real-to-complex conversion of the parallel single-bit samples from the serial-to-parallel converter to provide parallel I and Q output values at an intermediate frequency. The serial-to-parallel converter has shift register stages that provide a memory for use in functional realization of a boxcar filter and decimation-by-two in the digital quadrature mix. The digital quadrature mix utilizes logic to route and invert the parallel single-bit samples resulting in the parallel I and Q single-bit output values. Additional filter and decimate stages may be used to process the parallel I and Q single-bit output values.Type: GrantFiled: June 26, 2003Date of Patent: September 4, 2007Assignee: Rockwell Collins, Inc.Inventors: Billy D. Hart, Steven L. White
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Patent number: 7088793Abstract: An equalizer is used with complex modulation modems to reduce intersymbol interference. The equalizer includes an equalizer filter that receives an input data signal and adapts to compensate for the noisy communications channels to reduce intersymbol interference to the input signal. A branch metric computer demodulates the equalizer filter adapted input data signal. A decision device delivers an alpha value, starting phase information and confidence values from the demodulated input data signal. A gain determination function receives the confidence values and determines adaptation gain for the equalizer filter. A remodulator receives the alpha value and starting phase information and remodulates the alpha value and starting phase information into a remodulated data signal. A summing function compares the remodulated data signal to a delayed version of the input signal to generate an error signal for the equalizer filter to adjust the equalizer filter.Type: GrantFiled: April 17, 2002Date of Patent: August 8, 2006Assignee: Rockwell Collins, Inc.Inventors: Rodney L. Mickelson, Thomas L. Tapp, Steven L. White
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Patent number: 6968021Abstract: A bandwidth efficient advanced modulation waveform modem using concatenated iterative turbo coding and continuous phase modulation is disclosed. A demodulator in the modem has a turbo decoder and a decision feedback carrier and time tracking algorithm to track a carrier and adjust timing. The decision feedback carrier and time tracking algorithm may use an APP decoder as a decision device to provide symbol decisions at a high error rate and low latency for a coded input data stream. A symbol phase estimator produces a symbol phase error estimate from the symbol decisions. An erasure decision function decides which symbol decisions are correct and which symbol decisions are erasures. A carrier tracking function receives the symbol phase error estimates when the symbol decisions are correct and receives erasure inputs when the symbol decisions are erasures to maintain carrier tracking.Type: GrantFiled: September 24, 2001Date of Patent: November 22, 2005Assignee: Rockwell CollinsInventors: Steven L. White, Joseph C. Whited, Thomas L. Tapp, Rodney L. Mickelson
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Patent number: 6934327Abstract: Acquisition of a waveform such as a continuous-phase modulation (CPM) waveform is described. In one embodiment of the invention, the invention is directed to a method and apparatus for acquiring a waveform as defined by MIL-STD-188-181B including the preamble of such a waveform at a performance level defined by the standard. The present invention provides solutions to at least four primary issues presented in acquiring a CPM waveform such as the MIL-STD-188-181B compliant waveform. These primary problems include searching for the preamble, determination of the symbol rate, determination of an initial carrier frequency error (Doppler), determination of an initial carrier phase, and determination of the start-of-message to establish an absolute time marker within the waveform.Type: GrantFiled: April 23, 2001Date of Patent: August 23, 2005Assignee: Rockwell CollinsInventors: Joseph C. Whited, Steven L. White
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Patent number: 6708026Abstract: A programmable digital divider operates under the control of a division controller to derive a second synthesized frequency based on a first synthesized frequency. The programmable divider divides the first synthesized signal to derive the second synthesized signal. The division amount is an integer, but varies between integer values if necessary to achieve a non-integer average division value. The majority of the noise generated by the frequency synthesizer is generated away from the centerline frequency and is easily filtered by narrowband filter. The frequency synthesizer may optionally be incorporated into a modified phase-locked loop to generate the second synthesized signal. By using a digital divider, instead of a traditional phase-locked loop, these embodiments allow for integration of the frequency synthesizer onto an integrated circuit, thereby lowering cost and improving resistance to noise spurs. This approach is particularly suited to telecommunications applications.Type: GrantFiled: January 11, 2000Date of Patent: March 16, 2004Assignee: Ericsson Inc.Inventors: Nikolaus Klemmer, Antonio J. Montalvo, Steven L. White
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Patent number: 6477196Abstract: A method of excising one or more narrow-band interfering signals in a direct sequence spread spectrum receiver that performs a magnitude spectral analysis on baseband signals in a detection channel to determine which frequency bins in the spectral analysis output contain the interfering narrow-band signals by comparing the magnitude of the signals in the frequency bins to a threshold. The corrupted frequency bins are determined by the signal magnitudes exceeding the threshold and band reject filters excise the narrow-band signals in the signal channel in accordance with the corrupted frequency bins.Type: GrantFiled: August 30, 1999Date of Patent: November 5, 2002Assignee: Rockwell Collins, Inc.Inventors: Christopher J. Swanke, Steven L. White
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Patent number: 6265947Abstract: A power conserving phase-locked loop achieves power savings by adding a switch which selectively enables the bias current for the charge pump associated with the phase comparator of the phase-locked loop. The switch is connected by a logic circuit to a counter that tracks the expected arrival time of a signal edge of the reference signal. Immediately prior to the arrival of the expected signal edge, the switch is enabled, thereby creating and applying the bias current to activate the charge pump in the event that a correction is needed to maintain the “lock” in the phase-locked loop. When the signal edge passes, the bias current is turned off again before the arrival of the next signal edge. This switching may result in a ten percent duty cycle in the biasing current, resulting in approximately a ninety percent power savings.Type: GrantFiled: January 11, 2000Date of Patent: July 24, 2001Assignee: Ericsson Inc.Inventors: Nikolaus Klemmer, Steven L. White
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Patent number: 6265902Abstract: An improved digital phase detector is provided for detecting and compensating for a cycle slip between a reference signal and a frequency source signal, the reference and frequency source signals each comprising pulses, each pulse defined by a leading edge and a trailing edge. The digital phase detector includes a detector circuit for detecting a cycle slip where two successive leading edges of one of the reference and frequency source signals are received before a leading edge of the other signal is received. An output circuit is operatively coupled to the detector circuit for developing a correction signal responsive to said detecting.Type: GrantFiled: November 2, 1999Date of Patent: July 24, 2001Assignee: Ericsson Inc.Inventors: Nikolaus Klemmer, Steven L. White
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Patent number: 6208212Abstract: A delay cell comprises a fast delay stage including a differential amplifier for connection to a differential input. A slow delay stage includes a differential amplifier connected in parallel with the fast delay stage differential amplifier and having capacitance means for setting a delay amount. A current source develops a bias current. A current switch is connected between the current source and the fast delay stage and the slow delay stage to switch the bias current between the fast delay stage and the slow delay stage. An output circuit is connected to the fast and slow delay stages for developing a differential output delayed relative to the differential input responsive to a ratio between fast delay stage current and slow delay stage current.Type: GrantFiled: March 11, 1999Date of Patent: March 27, 2001Assignee: Ericsson Inc.Inventor: Steven L. White
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Patent number: 5003639Abstract: The invention relates to a protector for cap visors consisting of a flexible sheet of soil resistant or washable material having ends and lateral sides which is folded over the visor periphery and the material includes fastening cords attached to clips which are releasably affixed to the edges of the visor adjacent the cap headband. The protective device covers the majority of the visor and by the use of colors, decorations or advertising the protector ascetically adds to the cap appearance.Type: GrantFiled: November 20, 1989Date of Patent: April 2, 1991Inventor: Steven L. White