Patents by Inventor Steven Langdon

Steven Langdon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9425052
    Abstract: Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. For example, a carbon species may be incorporated by ion implantation into the active region of a P-channel transistor and an N-channel transistor after selectively forming a threshold adjusted semiconductor material for the P-channel transistor, while the active region of the N-channel transistor is still masked.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: August 23, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Jan Hoentschel, Steven Langdon
  • Publication number: 20150228490
    Abstract: Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. For example, a carbon species may be incorporated by ion implantation into the active region of a P-channel transistor and an N-channel transistor after selectively forming a threshold adjusted semiconductor material for the P-channel transistor, while the active region of the N-channel transistor is still masked.
    Type: Application
    Filed: April 28, 2015
    Publication date: August 13, 2015
    Inventors: Thilo Scheiper, Jan Hoentschel, Steven Langdon
  • Patent number: 9048336
    Abstract: Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. For example, a carbon species may be incorporated by ion implantation into the active region of a P-channel transistor and an N-channel transistor after selectively forming a threshold adjusted semiconductor material for the P-channel transistor, while the active region of the N-channel transistor is still masked.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: June 2, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Thilo Scheiper, Jan Hoentschel, Steven Langdon
  • Patent number: 8664068
    Abstract: The drain and source regions may at least be partially formed by in situ doped epitaxially grown semiconductor materials for complementary transistors in sophisticated semiconductor devices designed for low power and high performance applications. To this end, cavities may be refilled with in situ doped semiconductor material, which in some illustrative embodiments also provides a desired strain in the channel regions of the complementary transistors.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: March 4, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Jan Hoentschel, Stefan Flachowsky, Steven Langdon, Thilo Scheiper
  • Patent number: 8586440
    Abstract: Methods are provided for fabricating integrated circuits using non-oxidizing resist removal. In accordance with one embodiment the method includes forming a gate electrode structure overlying a semiconductor substrate and applying and patterning a layer of resist to expose a portion of the semiconductor substrate adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate using the gate electrode structure and the layer of resist as an implant mask. The layer of resist is removed in a non-oxidizing ambient and the implanted conductivity determining ions are activated by thermal annealing.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: November 19, 2013
    Assignee: GLOBALFOUNDRIES, Inc.
    Inventors: Stefan Flachowsky, Steven Langdon, Thomas Feudel
  • Patent number: 8508001
    Abstract: Disclosed herein is a semiconductor device that includes a semiconducting substrate and a work-function adjusting layer positioned at least partially in the semiconducting substrate, the work-function adjusting layer having a middle section, opposing ends and an end region located proximate each of said opposing ends and a gate electrode positioned above the work-function adjusting layer. Each of the end regions has a maximum thickness that is at least 25% greater than an average thickness of the middle section of the work-function adjusting layer.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: August 13, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven Langdon, Stefan Flachowsky, Thilo Scheiper
  • Patent number: 8501601
    Abstract: When forming sophisticated transistors, the channel region may be provided such that the gradient of the band gap energy of the channel material may result in superior charge carrier velocity. For example, a gradient in concentration of germanium, carbon and the like may be implemented along the channel length direction, thereby obtaining higher transistor performance.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: August 6, 2013
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Thilo Scheiper, Steven Langdon, Jan Hoentschel
  • Publication number: 20130029464
    Abstract: Methods are provided for fabricating integrated circuits using non-oxidizing resist removal. In accordance with one embodiment the method includes forming a gate electrode structure overlying a semiconductor substrate and applying and patterning a layer of resist to expose a portion of the semiconductor substrate adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate using the gate electrode structure and the layer of resist as an implant mask. The layer of resist is removed in a non-oxidizing ambient and the implanted conductivity determining ions are activated by thermal annealing.
    Type: Application
    Filed: July 27, 2011
    Publication date: January 31, 2013
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stefan Flachowsky, Steven Langdon, Thomas Feudel
  • Publication number: 20120193708
    Abstract: When forming sophisticated transistors, the channel region may be provided such that the gradient of the band gap energy of the channel material may result in superior charge carrier velocity. For example, a gradient in concentration of germanium, carbon and the like may be implemented along the channel length direction, thereby obtaining higher transistor performance.
    Type: Application
    Filed: September 22, 2011
    Publication date: August 2, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Stefan Flachowsky, Thilo Scheiper, Steven Langdon, Jan Hoentschel
  • Publication number: 20120153399
    Abstract: The drain and source regions may at least be partially formed by in situ doped epitaxially grown semiconductor materials for complementary transistors in sophisticated semiconductor devices designed for low power and high performance applications. To this end, cavities may be refilled with in situ doped semiconductor material, which in some illustrative embodiments also provides a desired strain in the channel regions of the complementary transistors.
    Type: Application
    Filed: July 28, 2011
    Publication date: June 21, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Jan Hoentschel, Stefan Flachowsky, Steven Langdon, Thilo Scheiper
  • Publication number: 20120049293
    Abstract: Performance and/or uniformity of sophisticated transistors may be enhanced by incorporating a carbon species in the active regions of the transistors prior to forming complex high-k metal gate electrode structures. For example, a carbon species may be incorporated by ion implantation into the active region of a P-channel transistor and an N-channel transistor after selectively forming a threshold adjusted semiconductor material for the P-channel transistor, while the active region of the N-channel transistor is still masked.
    Type: Application
    Filed: July 20, 2011
    Publication date: March 1, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Thilo SCHEIPER, Jan HOENTSCHEL, Steven LANGDON
  • Publication number: 20120049291
    Abstract: In sophisticated semiconductor devices, resistors may be provided together with high-k metal gate electrode structures by using a polycrystalline silicon material without requiring a deterioration of the crystalline nature and thus conductivity of a conductive metal-containing cap material that is used in combination with the high-k dielectric gate material. In this manner, superior uniformity of the resistance values may be obtained, while at the same time reducing the overall process complexity.
    Type: Application
    Filed: July 18, 2011
    Publication date: March 1, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Thilo Scheiper, Steven Langdon