Patents by Inventor Steven Lee Shrader

Steven Lee Shrader has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9703625
    Abstract: A method for detecting a data bit inversion (DBI) error in a memory system is disclosed. The method and system comprise calculating an error correcting code (ECC) from each of the 8 beats of a burst of data such that no more than one bit per byte is included in each ECC calculation. The method and system further include determining if there is an inversion of one byte in the burst.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: July 11, 2017
    Assignee: Cadence Design Systems, Inc.
    Inventors: Marc Greenberg, Steven Lee Shrader
  • Patent number: 7143315
    Abstract: Fault tolerant data storage systems and methods of operating a fault tolerant data storage system are presented. In one aspect of the invention, a fault tolerant data storage system comprises: a plurality of coupled components individually including: an interface adapted to couple with a data connection and to selectively receive a plurality of transactions from the data connection; transaction processing circuitry coupled with the interface and configured to process transactions received from the interface; and analysis circuitry configured to detect error conditions within the transactions and to prevent entry of transactions individually including an error condition into the respective component responsive to the detection.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: November 28, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert A. Rust, Barry J. Oldfield, Steven Lee Shrader, Christine Grund, Christopher W. Johansson
  • Patent number: 6801954
    Abstract: A controller is presented comprising one or more initiators coupled to one or more targets via a transaction bus and a corresponding number of data busses. The initiator(s) receive transaction requests from external logic, buffer the transaction and assign it a unique identifier, which is passed to an appropriate target via the transaction bus. The targets receive and queue the unique identifier until it can process the transaction, at which time it prompts the initiator to provide it the buffered transaction via a data bus dedicated to the target.
    Type: Grant
    Filed: February 25, 2000
    Date of Patent: October 5, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert A. Rust, Barry J. Oldfield, Christine Grund, Christopher W. Johansson, Steven Lee Shrader
  • Publication number: 20040153735
    Abstract: Fault tolerant data storage systems and methods of operating a fault tolerant data storage system are presented. In one aspect of the invention, a fault tolerant data storage system comprises: a plurality of coupled components individually including: an interface adapted to couple with a data connection and to selectively receive a plurality of transactions from the data connection; transaction processing circuitry coupled with the interface and configured to process transactions received from the interface; and analysis circuitry configured to detect error conditions within the transactions and to prevent entry of transactions individually including an error condition into the respective component responsive to the detection.
    Type: Application
    Filed: October 16, 2003
    Publication date: August 5, 2004
    Inventors: Robert A. Rust, Barry J. Oldfield, Steven Lee Shrader, Christine Grund, Christopher W. Johansson
  • Patent number: 6647516
    Abstract: Fault tolerant data storage systems and methods of operating a fault tolerant data storage system are presented. In one aspect of the invention, a fault tolerant data storage system comprises: a plurality of coupled components individually including: an interface adapted to couple with a data connection and to selectively receive a plurality of transactions from the data connection; transaction processing circuitry coupled with the interface and configured to process transactions received from the interface; and analysis circuitry configured to detect error conditions within the transactions and to prevent entry of transactions individually including an error condition into the respective component responsive to the detection.
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: November 11, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert A. Rust, Barry J. Oldfield, Steven Lee Shrader, Christine Grund, Christopher W. Johansson