Abstract: A priority encoder and a processing device having the priority encoder. The priority encoder includes a port selector for generating a plurality of prioritized read requests based on a plurality of write requests from a plurality of processing devices and a predetermined priority assigned to each of the plurality of processing devices, one of the plurality of processing devices being selected based on the plurality of prioritized read requests; and a port latch for holding the values of the prioritized read requests to enable one of a plurality of communication ports unless the prioritized read requests are changed, each communication port for communicating with one of the processing devices to read data from the processing device.

Abstract: A method of integrated circuit simulation comprising the steps of providing a voltage lookup table having predetermined drain voltage data for a given transistor type, providing a voltage lookup table having predetermined gate voltage data for a given transistor type. Providing a temperature lookup table having predetermined temperature data. Providing a transistor lookup table having predetermined current and temperature data. Simulating operation of an integrated circuit by, for each transistor in the integrated circuit, determining a current value through the transistor in dependence upon one of the predetermined voltage data values and one of the predetermined temperature data values; and comparing the current value calculated to the current value obtained previously; and updating active transistor list detecting a change in the current value. Then incrementing a simulation time step and repeating simulation steps for all transistors.

Abstract: The invention provides a method and apparatus for eliminating the stack overflow and underflow in a dual stack computer 100 while remaining fully operational in case of single event upset caused by radiation and a method and apparatus for eliminating stack overflow and underflow by replacing a conventional stack with a circular stack array 125B coupled to a plurality of multiplexers 205a-h to function in a circular repeating pattern. The method of the invention provides for the stack to remain operational in the event of single event upset by using one hot logic multiplexers 205a-h. Thus in case of single event upset, where the logic state of the control signals can be corrupted such that at a given time both the push or pop control signals are active, the multiplexers will not shift the data either upward or downward in the data stack 145 and the return stack 120 and prevents the processor system 100 from entering into an unknown state.

Abstract: A zero prediction method and apparatus for use in a reduced instruction set computer. The zero predictor 115 in use is connected by a controller 110 to an arithmetic unit 120. Different embodiments of the invention for use in addition include inverters 205 connected via incrementers 220 to comparators 235 for subtraction and comparators 235 for decrementation. The method includes determination 915 of which arithmetic operation to be performed, activation 925, 950 and 975 of a suitable zero prediction method for the operation along with the operation subtraction 930, addition 955 and decrementation 980. If a zero is detected, operations 930, 955 and 980 are deactivated.

Abstract: A carry select adder to add two binary addends to produce a binary sum. In a first section a first addition block adds 6-bit addend slices having 3-bit lower-half and higher-half slices. A first adder block receives and adds the lower-half slices and outputs an adder-carry-out and a 3-bit lower-half value. A zero-carry-loaded second adder block receives and adds the higher-half slices and outputs a 4-bit zero-related intermediate-value. A one-carry-loaded third adder block receives and adds the higher-half slices and outputs a 4-bit one-related intermediate-value. A 4-bit multiplexer then passes either the zero-related intermediate-value or the one-related intermediate-value as a 1-bit section-carry-out and a 3-bit higher-half value based on the adder-carry-out, wherein the higher-half value and the lower-half value form a 6-bit sum slice corresponding to the 6-bit addend slices.