Patents by Inventor Steven Leibiger
Steven Leibiger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9117845Abstract: In one general aspect, a method can include implanting a first dopant, simultaneously, in a portion of a laterally diffused metal oxide semiconductor (LDMOS) device and in a portion of a resistor device included in a semiconductor device. The method can also include implanting a second dopant, simultaneously, in a portion of the LDMOS device and in a portion of a bipolar junction transistor (BJT) device in the semiconductor device.Type: GrantFiled: January 25, 2013Date of Patent: August 25, 2015Assignee: Fairchild Semiconductor CorporationInventors: Christopher Nassar, Sunglyong Kim, Steven Leibiger, James Hall
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Patent number: 8987107Abstract: In one general aspect, a semiconductor processing method can include forming an N-type silicon region disposed within a P-type silicon substrate. The method can also include forming a field oxide (FOX) layer in the P-type silicon substrate where the FOX layer includes an opening exposing at least a portion of the N-type silicon region. The method can further include forming a reduced surface field (RESURF) oxide (ROX) layer having a first portion disposed on the exposed N-type silicon region and a second portion disposed on the FOX layer where the ROX layer includes a first dielectric layer in contact with the exposed N-type silicon region and a second dielectric layer disposed on the first dielectric layer. The method can further include forming a doped polysilicon layer having a first portion disposed on the first portion of the ROX layer and a second portion disposed on the second portion of the ROX layer.Type: GrantFiled: February 19, 2013Date of Patent: March 24, 2015Assignee: Fairchild Semiconductor CorporationInventors: Daniel Hahn, Steven Leibiger, Sunglyong Kim, Christopher Nassar, James Hall
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Patent number: 8878275Abstract: In one general aspect, an apparatus can include a channel region disposed in a semiconductor substrate, a gate dielectric disposed on the channel region and a drift region disposed in the semiconductor substrate adjacent to the channel region. The apparatus can further include a field plate having an end portion disposed between a top surface of the semiconductor substrate and the gate dielectric The end portion can include a surface in contact with the gate dielectric, the surface having a first portion aligned along a first plane non-parallel to a second plane along which a second portion of the surface is aligned, the first plane being non-parallel to the top surface of the semiconductor substrate and the second plane being non-parallel to the top surface of the semiconductor substrate.Type: GrantFiled: February 18, 2013Date of Patent: November 4, 2014Assignee: Fairchild Semiconductor CorporationInventors: Sunglyong Kim, Mark Schmidt, Christopher Nassar, Steven Leibiger
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Patent number: 8822296Abstract: Semiconductor devices and methods for making such devices are described. The semiconductor devices are made by providing a semiconductor substrate with an active region, providing a bulk oxide layer in a non-active portion of the substrate, the bulk oxide layer having a first thickness in a protected area of the device, providing a plate oxide layer over the bulk oxide layer and over the substrate in the active region, forming a gate structure on the active region of the substrate, and forming a self-aligned silicide layer on a portion of the substrate and the gate structure, wherein the final thickness of the bulk oxide layer in the protected area after these processes remains substantially the same as the first thickness. The thickness of the bulk oxide layer can be increased without any additional processing steps or any additional processing cost. Other embodiments are described.Type: GrantFiled: October 31, 2012Date of Patent: September 2, 2014Assignee: Fairchild Semiconductor CorporationInventors: Sunglyong Kim, Steven Leibiger, Christopher Nassar
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Publication number: 20140231952Abstract: In one general aspect, a semiconductor processing method can include forming an N-type silicon region disposed within a P-type silicon substrate. The method can also include forming a field oxide (FOX) layer in the P-type silicon substrate where the FOX layer includes an opening exposing at least a portion of the N-type silicon region. The method can further include forming a reduced surface field (RESURF) oxide (ROX) layer having a first portion disposed on the exposed N-type silicon region and a second portion disposed on the FOX layer where the ROX layer includes a first dielectric layer in contact with the exposed N-type silicon region and a second dielectric layer disposed on the first dielectric layer. The method can further include forming a doped polysilicon layer having a first portion disposed on the first portion of the ROX layer and a second portion disposed on the second portion of the ROX layer.Type: ApplicationFiled: February 19, 2013Publication date: August 21, 2014Applicant: Fairchild Semiconductor CorporationInventors: Daniel Hahn, Steven Leibiger, Sunglyong Kim, Christopher Nassar, James Hall
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Publication number: 20140231911Abstract: In one general aspect, an apparatus can include a channel region disposed in a semiconductor substrate, a gate dielectric disposed on the channel region and a drift region disposed in the semiconductor substrate adjacent to the channel region. The apparatus can further include a field plate having an end portion disposed between a top surface of the semiconductor substrate and the gate dielectric The end portion can include a surface in contact with the gate dielectric, the surface having a first portion aligned along a first plane non-parallel to a second plane along which a second portion of the surface is aligned, the first plane being non-parallel to the top surface of the semiconductor substrate and the second plane being non-parallel to the top surface of the semiconductor substrate.Type: ApplicationFiled: February 18, 2013Publication date: August 21, 2014Applicant: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: Sunglyong Kim, Mark Schmidt, Christopher Nassar, Steven Leibiger
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Publication number: 20140213024Abstract: In one general aspect, a method can include implanting a first dopant, simultaneously, in a portion of a laterally diffused metal oxide semiconductor (LDMOS) device and in a portion of a resistor device included in a semiconductor device. The method can also include implanting a second dopant, simultaneously, in a portion of the LDMOS device and in a portion of a bipolar junction transistor (BJT) device in the semiconductor device.Type: ApplicationFiled: January 25, 2013Publication date: July 31, 2014Applicant: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: CHRISTOPHER NASSAR, SUNGLYONG KIM, STEVEN LEIBIGER, JAMES HALL
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Publication number: 20140120694Abstract: Semiconductor devices and methods for making such devices are described. The semiconductor devices are made by providing a semiconductor substrate with an active region, providing a bulk oxide layer in a non-active portion of the substrate, the bulk oxide layer having a first thickness in a protected area of the device, providing a plate oxide layer over the bulk oxide layer and over the substrate in the active region, forming a gate structure on the active region of the substrate, and forming a self-aligned silicide layer on a portion of the substrate and the gate structure, wherein the final thickness of the bulk oxide layer in the protected area after these processes remains substantially the same as the first thickness. The thickness of the bulk oxide layer can be increased without any additional processing steps or any additional processing cost. Other embodiments are described.Type: ApplicationFiled: October 31, 2012Publication date: May 1, 2014Applicant: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: Sunglyong Kim, Steven Leibiger, Christopher Nassar
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Patent number: 8080847Abstract: In one embodiment of the present invention an array of power transistors on a semiconductor chip has repeating patterns of two “wave” gates which have alternating longer and shorter horizontal sections which are offset mirror images of each other together with a third straight horizontal section. Alternating source and drain regions lie between adjacent gates. Contacts are located adjacent each side of sections of the “wave” gates which connect the ends of the horizontal sections of the “wave” gates.Type: GrantFiled: April 8, 2009Date of Patent: December 20, 2011Assignee: Fairchild Semiconductor CorporationInventor: Steven Leibiger
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Patent number: 8076722Abstract: A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate with a drift region between source region and drain regions. The drift region includes a structure having a spaced trench capacitor extending between the source region and the drain region and a vertical stack extending between the source region and the drain region. When the device is in an on state, current flows between the source and drain regions; and, when the device is in an off/blocking state, the drift region is depleted into the stack.Type: GrantFiled: July 29, 2010Date of Patent: December 13, 2011Assignee: Fairchild Semiconductor CorporationInventors: Steven Leibiger, Gary Dolny
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Publication number: 20100323485Abstract: A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate with a drift region between source region and drain regions. The drift region includes a structure having a spaced trench capacitor extending between the source region and the drain region and a vertical stack extending between the source region and the drain region. When the device is in an on state, current flows between the source and drain regions; and, when the device is in an off/blocking state, the drift region is depleted into the stack.Type: ApplicationFiled: July 29, 2010Publication date: December 23, 2010Applicant: Fairchild Semiconductor CorporationInventors: Steven Leibiger, Gary Dolny
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Patent number: 7824999Abstract: A CMOS device with polysilicon protection tiles is shown in FIG. 2. LOCOS regions 12.1 and 12.2 separate adjacent active regions 16.1 from 16 and 18.1 from 18, respectively. On the upper surface of the LOCOS regions 12.1, 12.2 are polysilicon tiles 14.1, 14.2, respectively. At the corner of the gate polysilicon 14.3 and the polysilicon tiles 14.1 and 14.2 are oxide spacers 60.1-60.6. The polysilicon tiles 14.1, 14.2 have silicide layers 50.1, 50.2. Other silicide layers 50.4-50.6 are on the tops of the source, drain and polysilicon gate. An insulation layer 32 covers the substrate and metal contacts 36, 34, 38 extend from the surface of the layer 32 to the silicide layers on the source, gate and drain, respectively. The polysilicon tiles are made from the same layer of polysilicon as the gate and they are formed simultaneously with the gates. The intention of the polysilicon tiles is to reduce erosion of the field oxide between closely spaced active regions.Type: GrantFiled: January 22, 2008Date of Patent: November 2, 2010Assignee: Fairchild Semiconductor CorporationInventors: Steven Leibiger, Daniel J. Hahn
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Patent number: 7795671Abstract: A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate; a source region and a drain region provided in the substrate; wherein the source region and the drain region are laterally spaced from each other; and a drift region in the substrate between the source region and the drain region. The drift region includes a structure having at least two spaced trench capacitors extending between the source region and the drain region; and further includes a stack having at least a first region of a first conductivity type, a second region of a second conductivity type, and a third region of the first conductivity type, wherein the stack extends between the source region and the drain region and between the at least first and second trench capacitors and in electrical connection to the first and second trench capacitors.Type: GrantFiled: January 4, 2007Date of Patent: September 14, 2010Assignee: Fairchild Semiconductor CorporationInventors: Steven Leibiger, Gary Dolny
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Patent number: 7763939Abstract: An array of power transistors on a semiconductor chip has serpentine gates separated by alternating source and drain regions. The gates combine rounded ends and rectangular sections joining the rounded ends. This geometry allows the metallization, in which the upper and lower metal layers are substantially congruent with each other, to have a design width that can be increased or decreased with the changes in width matched by the length of the rectangular sections thus allowing flexibility in the design of the power transistors.Type: GrantFiled: May 23, 2008Date of Patent: July 27, 2010Assignee: Fairchild Semiconductor CorporationInventor: Steven Leibiger
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Publication number: 20090250765Abstract: In one embodiment of the present invention an array of power transistors on a semiconductor chip has repeating patterns of two “wave” gates which have alternating longer and shorter horizontal sections which are offset mirror images of each other together with a third straight horizontal section. Alternating source and drain regions lie between adjacent gates. Contacts are located adjacent each side of sections of the “wave” gates which connect the ends of the horizontal sections of the “wave” gates.Type: ApplicationFiled: April 8, 2009Publication date: October 8, 2009Inventor: Steven Leibiger
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Publication number: 20080290419Abstract: An array of power transistors on a semiconductor chip has serpentine gates separated by alternating source and drain regions. The gates combine rounded ends and rectangular sections joining the rounded ends. This geometry allows the metallization, in which the upper and lower metal layers are substantially congruent with each other, to have a design width that can be increased or decreased with the changes in width matched by the length of the rectangular sections thus allowing flexibility in the design of the power transistors.Type: ApplicationFiled: May 23, 2008Publication date: November 27, 2008Inventor: Steven Leibiger
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Publication number: 20080164506Abstract: A high voltage semiconductor device, such as a RESURF transistor, having improved properties, including reduced on state resistance. The device includes a semiconductor substrate; a source region and a drain region provided in the substrate; wherein the source region and the drain region are laterally spaced from each other; and a drift region in the substrate between the source region and the drain region. The drift region includes a structure having at least two spaced trench capacitors extending between the source region and the drain region; and further includes a stack having at least a first region of a first conductivity type, a second region of a second conductivity type, and a third region of the first conductivity type, wherein the stack extends between the source region and the drain region and between the at least first and second trench capacitors and in electrical connection to the first and second trench capacitors.Type: ApplicationFiled: January 4, 2007Publication date: July 10, 2008Inventors: Steven Leibiger, Gary Dolny
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Publication number: 20080113482Abstract: A CMOS device with polysilicon protection tiles is shown in FIG. 2. LOCOS regions 12.1 and 12.2 separate adjacent active regions 16.1 from 16 and 18.1 from 18, respectively. On the upper surface of the LOCOS regions 12.1, 12.2 are polysilicon tiles 14.1, 14.2, respectively. At the corner of the gate polysilicon 14.3 and the polysilicon tiles 14.1 and 14.2 are oxide spacers 60.1-60.6. The polysilicon tiles 14.1, 14.2 have silicide layers 50.1, 50.2. Other silicide layers 50.4-50.6 are on the tops of the source, drain and polysilicon gate. An insulation layer 32 covers the substrate and metal contacts 36, 34, 38 extend from the surface of the layer 32 to the silicide layers on the source, gate and drain, respectively. The polysilicon tiles are made from the same layer of polysilicon as the gate and they are formed simultaneously with the gates. The intention of the polysilicon tiles is to reduce erosion of the field oxide between closely spaced active regions.Type: ApplicationFiled: January 22, 2008Publication date: May 15, 2008Inventors: Steven Leibiger, Daniel Hahn
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Publication number: 20050275058Abstract: A CMOS device with polysilicon protection tiles is shown in FIG. 2. LOCOS regions 12.1 and 12.2 separate adjacent active regions 16.1 from 16 and 18.1 from 18, respectively. On the upper surface of the LOCOS regions 12.1, 12.2 are polysilicon tiles 14.1, 14.2, respectively. At the corner of the gate polysilicon 14.3 and the polysilicon tiles 14.1 and 14.2 are oxide spacers 60.1-60.6. The polysilicon tiles 14.1, 14.2 have silicide layers 50.1, 50.2. Other silicide layers 50.4-50.6 are on the tops of the source, drain and polysilicon gate. An insulation layer 32 covers the substrate and metal contacts 36, 34, 38 extend from the surface of the layer 32 to the silicide layers on the source, gate and drain, respectively. The polysilicon tiles are made from the same layer of polysilicon as the gate and they are formed simultaneously with the gates. The intention of the polysilicon tiles is to reduce erosion of the field oxide between closely spaced active regions.Type: ApplicationFiled: May 28, 2004Publication date: December 15, 2005Inventors: Steven Leibiger, Daniel Hahn
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Patent number: 6100125Abstract: An ESD protection device including a transistor structure with resistive regions located within active areas thereof. The transistor structure is formed of one or more MOS transistors, preferably N-type MOS transistors. The drain regions of the transistors are modified to reduce the conductivity of those resistive regions by preventing high carrier concentration implants in one or more sections of the drain regions. This is achieved by modifying an N LDD mask and the steps related thereto, as well as a silicide exclusion mask and the steps related thereto. The modifications result in the omission of N LDD dopant from the area immediately adjacent to the underlying channel. In addition, portions of a spacer oxide remain over the drain region to be formed. Subsequent implant and siliciding steps are effectively blocked by the spacer oxide that remains, leaving a low-density drain (LDD) charge carrier concentration in those regions, except where omitted.Type: GrantFiled: September 25, 1998Date of Patent: August 8, 2000Assignee: Fairchild Semiconductor Corp.Inventors: Ronald Brett Hulfachor, Steven Leibiger, Michael Harley-Stead, Daniel James Hahn