Abstract: One disclosed embodiment may comprise an interpolation system that includes an interpolator that interpolates between a selected phase from a preceding cycle and a selected phase from a current cycle to provide an interpolated phase for the current cycle. An edge of the interpolated phase for the current cycle has reduced jitter relative to an edge of a corresponding phase of the current cycle. A delay system delays a plurality of other phases of the current cycle to provide delayed other phases, the delayed other phases and the interpolated phase for the current cycle collectively defining a set of adjusted phases for the current cycle.

Abstract: Techniques are disclosed for increasing reliability of an integrated circuit. In one embodiment, an integrated circuit includes core chip circuitry. The integrated circuit includes means for increasing a power supply voltage V provided to the core chip circuitry, such as by increasing the voltage V to a maximum value. The integrated circuit also includes means for identifying a clock frequency F for which F<Pmax/(CV2), where C is a switching capacitance and where Pmax is a predetermined maximum power consumption of the core chip circuitry. The integrated circuit also includes means for providing a clock signal having frequency F to the circuit.