Patents by Inventor Steven Lorenz Wright
Steven Lorenz Wright has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230197658Abstract: A flip chip device and methods for fabrication are provided. An interconnect layer for a device include a plurality of solder bumps arranged within the interconnect layer. A first subset of the plurality of solder bumps has a first cross-sectional area, where the first subset is arranged along a first position at a first edge of the interconnect layer. A second subset of the plurality of solder bumps has a second cross-sectional area, where the second subset is arranged at a second position of the interconnect layer. A third subset of the plurality of solder bumps is arranged between the first position and the second position, where the third subset has a plurality of cross-sectional areas.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Inventors: Kamal K. SIKKA, Charles Leon ARVIN, Thomas Edward LOMBARDI, Piyas Bal CHOWDHURY, Alfred GRILL, Steven Lorenz WRIGHT
-
Publication number: 20230197705Abstract: Embodiments of one or more high bandwidth chips (HB chips), e.g., high bandwidth memories (HBMs), are mounted on a module substrate. The HB chips/HBMs each have one or more HBM parallel communication interfaces (HB chip PHYs or HBM PHYs, respectively) that are connected to a companion PHY through a compatible companion PHY parallel connection that enable communication between the HBM PHY and the companion PHY. A companion PHY parallel link connection connects to a SERDES parallel connection of a SERDES. The SERDES converts parallel data/information at the SERDES parallel connection to serial data information at a SERDES serial connection, and visa-versa, that enables efficient high bandwidth data transfer over longer distances. Alternative embodiments are disclosed.Type: ApplicationFiled: December 16, 2021Publication date: June 22, 2023Inventors: Joshua M. Rubin, Steven Lorenz Wright, Arvind Kumar, Mounir Meghelli
-
Patent number: 11587896Abstract: A pillar structure is provided. The pillar structure includes a plurality of pillars. Each of the pillars include a capping material layer formed in a pit etched into a template wafer, a conductive plug formed on the capping material layer, a base layer formed on the conductive plug, and an attach material layer formed on the base layer. The pillars are joined vertically together to form the pillar structure.Type: GrantFiled: December 9, 2020Date of Patent: February 21, 2023Assignee: International Business Machines CorporationInventors: Joshua M. Rubin, Yang Liu, Steven Lorenz Wright, Paul S. Andry
-
Patent number: 11574875Abstract: A multi-chip package structure includes a chip interconnect bridge, a fan-out redistribution layer structure, a first integrated circuit chip, and a second integrated circuit chip. The chip interconnect bridge includes contact pads disposed on a top side of the chip interconnect bridge. The fan-out redistribution layer structure is disposed around sidewalls of the chip interconnect bridge and over the top side of the chip interconnect bridge. The first and second integrated circuit chips are direct chip attached to an upper surface of the fan-out redistribution layer structure, wherein the fan-out redistribution layer structure includes input/output connections between the contact pads on the top side of the chip interconnect bridge and the first and second integrated circuit chips.Type: GrantFiled: May 13, 2021Date of Patent: February 7, 2023Assignee: International Business Machines CorporationInventors: Joshua M. Rubin, Steven Lorenz Wright, Lawrence A. Clevenger
-
Publication number: 20220181286Abstract: A pillar structure is provided. The pillar structure includes a plurality of pillars. Each of the pillars include a capping material layer formed in a pit etched into a template wafer, a conductive plug formed on the capping material layer, a base layer formed on the conductive plug, and an attach material layer formed on the base layer. The pillars are joined vertically together to form the pillar structure.Type: ApplicationFiled: December 9, 2020Publication date: June 9, 2022Inventors: Joshua M. Rubin, Yang Liu, Steven Lorenz Wright, Paul S. Andry
-
Patent number: 11164817Abstract: Techniques are provided for constructing multi-chip package structures. For example, a multi-chip package structure includes a package substrate, an interconnect bridge device, a first chip package, and a second chip package. The first chip package includes a first redistribution layer structure, and a first integrated circuit chip connected to the first redistribution layer structure. The first redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The second chip package includes a second redistribution layer structure, and a second integrated circuit chip connected to the second redistribution layer structure. The second redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The interconnect bridge device includes wiring to provide package-to-package connections between the first and second chip packages.Type: GrantFiled: November 1, 2019Date of Patent: November 2, 2021Assignee: International Business Machines CorporationInventors: Joshua M. Rubin, Kamal K. Sikka, Steven Lorenz Wright, Lawrence A. Clevenger
-
Patent number: 11133259Abstract: A multi-chip package structure includes a package substrate, an interconnect bridge device, first and second integrated circuit chips, and a connection structure. The first integrated circuit chip is flip-chip attached to at least the interconnect bridge device. The second integrated circuit chip is flip-chip attached to the interconnect bridge device and to the package substrate. The interconnect bridge device includes (i) wiring that is configured to provide chip-to-chip connections between the first and second integrated circuit chips and (ii) an embedded power distribution network that is configured to distribute at least one of a positive power supply voltage and a negative power supply voltage to at least one of the first and second integrated circuit chips attached to the interconnect bridge device. The connection structure (e.g., wire bond, injection molded solder, etc.) connects the embedded power distribution network to a power supply voltage contact of the package substrate.Type: GrantFiled: December 12, 2019Date of Patent: September 28, 2021Assignee: International Business Machines CorporationInventors: Joshua M. Rubin, Arvind Kumar, Lawrence A. Clevenger, Steven Lorenz Wright, Wiren Dale Becker, Xiao Hu Liu
-
Patent number: 11114410Abstract: Techniques are provided for constructing multi-chip package structures using pre-positioned interconnect bridge devices that are fabricated on a bridge wafer. For example, integrated circuit chips are mounted to a bridge wafer which is formed to have a plurality of pre-positioned interconnect bridge devices, wherein at least two integrated circuit chips are joined to each interconnect bridge device, and wherein each interconnect bridge device includes wiring to provide chip-to-chip connections between the integrated circuit chips connected to the interconnect bridge device. A wafer-level molding layer is formed on the bridge wafer to encapsulate the integrated circuit chips mounted to the bridge wafer. The interconnect bridge devices are released from the bridge wafer. The wafer-level molding layer is then diced to form a plurality of individual multi-chip modules.Type: GrantFiled: November 27, 2019Date of Patent: September 7, 2021Assignee: International Business Machines CorporationInventors: Joshua M. Rubin, Steven Lorenz Wright, Lawrence A. Clevenger
-
Publication number: 20210265275Abstract: A multi-chip package structure includes a chip interconnect bridge, a fan-out redistribution layer structure, a first integrated circuit chip, and a second integrated circuit chip. The chip interconnect bridge includes contact pads disposed on a top side of the chip interconnect bridge. The fan-out redistribution layer structure is disposed around sidewalls of the chip interconnect bridge and over the top side of the chip interconnect bridge. The first and second integrated circuit chips are direct chip attached to an upper surface of the fan-out redistribution layer structure, wherein the fan-out redistribution layer structure includes input/output connections between the contact pads on the top side of the chip interconnect bridge and the first and second integrated circuit chips.Type: ApplicationFiled: May 13, 2021Publication date: August 26, 2021Inventors: Joshua M. Rubin, Steven Lorenz Wright, Lawrence A. Clevenger
-
Patent number: 11094637Abstract: A multi-chip package structure includes a chip interconnect bridge, a fan-out redistribution layer structure, a first integrated circuit chip, and a second integrated circuit chip. The chip interconnect bridge includes contact pads disposed on a top-side of the chip interconnect bridge. The fan-out redistribution layer structure is disposed around sidewalls of the chip interconnect bridge and over the top-side of the chip interconnect bridge. The first and second integrated circuit chips are direct chip attached to an upper surface of the fan-out redistribution layer structure, wherein the fan-out redistribution layer structure includes input/output connections between the contact pads on the top-side of the chip interconnect bridge and the first and second integrated circuit chips.Type: GrantFiled: November 6, 2019Date of Patent: August 17, 2021Assignee: International Business Machines CorporationInventors: Joshua M. Rubin, Steven Lorenz Wright, Lawrence A. Clevenger
-
Publication number: 20210183773Abstract: A multi-chip package structure includes a package substrate, an interconnect bridge device, first and second integrated circuit chips, and a connection structure. The first integrated circuit chip is flip-chip attached to at least the interconnect bridge device. The second integrated circuit chip is flip-chip attached to the interconnect bridge device and to the package substrate. The interconnect bridge device includes (i) wiring that is configured to provide chip-to-chip connections between the first and second integrated circuit chips and (ii) an embedded power distribution network that is configured to distribute at least one of a positive power supply voltage and a negative power supply voltage to at least one of the first and second integrated circuit chips attached to the interconnect bridge device. The connection structure (e.g., wire bond, injection molded solder, etc.) connects the embedded power distribution network to a power supply voltage contact of the package substrate.Type: ApplicationFiled: December 12, 2019Publication date: June 17, 2021Inventors: Joshua M. Rubin, Arvind Kumar, Lawrence A. Clevenger, Steven Lorenz Wright, Wiren Dale Becker, Xiao Hu Liu
-
Publication number: 20210159211Abstract: Techniques are provided for constructing multi-chip package structures using pre-positioned interconnect bridge devices that are fabricated on a bridge wafer. For example, integrated circuit chips are mounted to a bridge wafer which is formed to have a plurality of pre-positioned interconnect bridge devices, wherein at least two integrated circuit chips are joined to each interconnect bridge device, and wherein each interconnect bridge device includes wiring to provide chip-to-chip connections between the integrated circuit chips connected to the interconnect bridge device. A wafer-level molding layer is formed on the bridge wafer to encapsulate the integrated circuit chips mounted to the bridge wafer. The interconnect bridge devices are released from the bridge wafer. The wafer-level molding layer is then diced to form a plurality of individual multi-chip modules.Type: ApplicationFiled: November 27, 2019Publication date: May 27, 2021Inventors: Joshua M. Rubin, Steven Lorenz Wright, Lawrence A. Clevenger
-
Publication number: 20210134724Abstract: Techniques are provided for constructing multi-chip package structures. For example, a multi-chip package structure includes a package substrate, an interconnect bridge device, a first chip package, and a second chip package. The first chip package includes a first redistribution layer structure, and a first integrated circuit chip connected to the first redistribution layer structure. The first redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The second chip package includes a second redistribution layer structure, and a second integrated circuit chip connected to the second redistribution layer structure. The second redistribution layer structure is connected to the interconnect bridge device and to the package substrate. The interconnect bridge device includes wiring to provide package-to-package connections between the first and second chip packages.Type: ApplicationFiled: November 1, 2019Publication date: May 6, 2021Inventors: Joshua M. Rubin, Kamal K. Sikka, Steven Lorenz Wright, Lawrence A. Clevenger
-
Publication number: 20210134728Abstract: A multi-chip package structure includes a chip interconnect bridge, a fan-out redistribution layer structure, a first integrated circuit chip, and a second integrated circuit chip. The chip interconnect bridge includes contact pads disposed on a top-side of the chip interconnect bridge. The fan-out redistribution layer structure is disposed around sidewalls of the chip interconnect bridge and over the top-side of the chip interconnect bridge. The first and second integrated circuit chips are direct chip attached to an upper surface of the fan-out redistribution layer structure, wherein the fan-out redistribution layer structure includes input/output connections between the contact pads on the top-side of the chip interconnect bridge and the first and second integrated circuit chips.Type: ApplicationFiled: November 6, 2019Publication date: May 6, 2021Inventors: Joshua M. Rubin, Steven Lorenz Wright, Lawrence A. Clevenger
-
Patent number: 10396220Abstract: A semiconductor structure includes a thin-film device layer, an optoelectronic device disposed in the thin-film device layer, and a surrogate substrate permanently attached to the thin film device layer. The optoelectronic device is excitable by light at an application wavelength. The surrogate substrate is optically transparent and has a thermal conductivity of at least 300 W/m-K. The surrogate substrate has a volume of substrate removed therefrom to form a via. Light passes through the via and at least some of the surrogate substrate prior to reaching the optoelectronic device.Type: GrantFiled: January 14, 2019Date of Patent: August 27, 2019Assignee: International Business Machines CorporationInventors: Bing Dang, John U. Knickerbocker, Steven Lorenz Wright, Cornelia Tsang Yang
-
Publication number: 20190148564Abstract: A semiconductor structure includes a thin-film device layer, an optoelectronic device disposed in the thin-film device layer, and a surrogate substrate permanently attached to the thin film device layer. The optoelectronic device is excitable by light at an application wavelength. The surrogate substrate is optically transparent and has a thermal conductivity of at least 300 W/m-K. The surrogate substrate has a volume of substrate removed therefrom to form a via. Light passes through the via and at least some of the surrogate substrate prior to reaching the optoelectronic device.Type: ApplicationFiled: January 14, 2019Publication date: May 16, 2019Inventors: Bing DANG, John U. KNICKERBOCKER, Steven Lorenz WRIGHT, Cornelia TSANG YANG
-
Patent number: 10243091Abstract: A semiconductor structure includes a thin-film device layer, an optoelectronic device disposed in the thin-film device layer, and a surrogate substrate permanently attached to the thin film device layer. The surrogate substrate is optically transparent and has a thermal conductivity of at least 300 W/m-K. The optoelectronic device excitable by visible light transmitted through the surrogate substrate.Type: GrantFiled: April 3, 2018Date of Patent: March 26, 2019Assignee: International Business Machines CorporationInventors: Bing Dang, John U. Knickerbocker, Steven Lorenz Wright, Cornelia Tsang Yang
-
Publication number: 20180226516Abstract: A semiconductor structure includes a thin-film device layer, an optoelectronic device disposed in the thin-film device layer, and a surrogate substrate permanently attached to the thin film device layer. The surrogate substrate is optically transparent and has a thermal conductivity of at least 300 W/m-K. The optoelectronic device excitable by visible light transmitted through the surrogate substrate.Type: ApplicationFiled: April 3, 2018Publication date: August 9, 2018Applicant: International Business Machines CorporationInventors: Bing DANG, John U. KNICKERBOCKER, Steven Lorenz WRIGHT, Cornelia TSANG YANG
-
Patent number: 10032943Abstract: A semiconductor structure includes a thin-film device layer, an optoelectronic device disposed in the thin-film device layer, and a surrogate substrate permanently attached to the thin film device layer. The surrogate substrate is optically transparent and has a thermal conductivity of at least 300 W/m-K. The optoelectronic device excitable by visible light transmitted through the surrogate substrate. A method of fabricating the semiconductor structure includes fabricating the optoelectronic device in a device layer thin-film of SiC on a silicon wafer of a first diameter, transferring the device layer thin-film of SiC from the silicon wafer, and permanently bonding the device layer thin-film to a SiC surrogate substrate of a second diameter.Type: GrantFiled: December 18, 2015Date of Patent: July 24, 2018Assignee: International Business Machines CorporationInventors: Bing Dang, John U. Knickerbocker, Steven Lorenz Wright, Cornelia Tsang Yang
-
Publication number: 20170179307Abstract: A semiconductor structure includes a thin-film device layer, an optoelectronic device disposed in the thin-film device layer, and a surrogate substrate permanently attached to the thin film device layer. The surrogate substrate is optically transparent and has a thermal conductivity of at least 300 W/m-K. The optoelectronic device excitable by visible light transmitted through the surrogate substrate. A method of fabricating the semiconductor structure includes fabricating the optoelectronic device in a device layer thin-film of SiC on a silicon wafer of a first diameter, transferring the device layer thin-film of SiC from the silicon wafer, and permanently bonding the device layer thin-film to a SiC surrogate substrate of a second diameter.Type: ApplicationFiled: December 18, 2015Publication date: June 22, 2017Inventors: Bing DANG, John U. KNICKERBOCKER, Steven Lorenz WRIGHT, Cornelia Tsang YANG