Patents by Inventor Steven LOVELESS

Steven LOVELESS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10748818
    Abstract: In various examples, a method and apparatus are provided to achieve dynamic biasing to mitigate electrical stress. Described examples include a device includes a first resistor portion having a first terminal and a second terminal, and a second resistor portion having a third terminal and a fourth terminal. The device also includes a well in a substrate proximate to the first resistor portion and the second resistor portion and an insulating layer between the well and the first resistor portion and the second resistor portion. The device also includes a transistor having a control terminal coupled to the second terminal of the first resistor portion and the third terminal of the second resistor portion, the transistor having a first current-handling terminal coupled to a first voltage and a second current-handling terminal coupled to a current source and to the well.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tathagata Chatterjee, Steven Loveless, James Robert Todd, Andrew Strachan
  • Publication number: 20200203230
    Abstract: In various examples, a method and apparatus are provided to achieve dynamic biasing to mitigate electrical stress. Described examples include a device includes a first resistor portion having a first terminal and a second terminal, and a second resistor portion having a third terminal and a fourth terminal. The device also includes a well in a substrate proximate to the first resistor portion and the second resistor portion and an insulating layer between the well and the first resistor portion and the second resistor portion. The device also includes a transistor having a control terminal coupled to the second terminal of the first resistor portion and the third terminal of the second resistor portion, the transistor having a first current-handling terminal coupled to a first voltage and a second current-handling terminal coupled to a current source and to the well.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Inventors: Tathagata Chatterjee, Steven Loveless, James Robert Todd, Andrew Strachan
  • Publication number: 20190204375
    Abstract: A system comprises a noise generator circuit and a noise envelope detector circuit. The noise generator circuit comprises a first amplifier including a single transistor pair that is operable to generate 1/f noise, an output amplifier coupled to the first amplifier and configured to generate a 1/f noise signal as a function of the 1/f noise. The noise envelope detector circuit comprises a low pass filter operable to pass low frequency signals of the 1/f noise signal as a filtered 1/f noise signal, and a second amplifier or a comparator coupled to the low pass filter and operable to output a direct current (DC) voltage signal according to an envelope of the filtered 1/f noise signal, where the DC voltage signal is a function of an envelope of the filtered 1/f noise signal.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Yuguo WANG, Steven LOVELESS, Tathagata CHATTERJEE, Jerry DOORENBOS