Abstract: The invention includes both devices and methods of production. A device in accordance with the invention includes a top surface and a bottom surface, a through wafer via extending from the top surface to the bottom surface, an optoelectronic structure and an ion implanted isolation moat, wherein the optoelectronic structure and the through wafer via are enclosed within the isolation moat. A method in accordance with the invention is a method of producing a device that includes the steps of forming an optoelectronic structure, forming a through wafer via, extending from a top surface to a bottom surface of the device and forming an ion implanted isolation moat, wherein the through wafer via and the optoelectronic structure are enclosed by the isolation moat.

Abstract: A high-speed optical transceiver for an integrated circuit (IC) includes a serializer-deserializer (SERDES) and a vertical cavity surface emitting laser (VCSEL) combined with a detector array. By covalently bonding the SERDES die to the IC, the two components can be processed simultaneously to produce a tightly aligned, high-speed data interface. The SERDES can be coupled to the VCSEL/detector array using a flex interconnect, or the VCSEL/detector array can also be covalently bonded to the IC or SERDES to maximize data bandwidth. The SERDES and VCSEL/detector array can also be produced in a single die using a process technology appropriate for both to maximize manufacturing efficiency.

Abstract: A high-speed optical transceiver for an integrated circuit (IC) includes a serializer-deserializer (SERDES) and a vertical cavity surface emitting laser (VCSEL) combined with a detector array. By covalently bonding the SERDES die to the IC, the two components can be processed simultaneously to produce a tightly aligned, high-speed data interface. The SERDES can be coupled to the VCSEL/detector array using a flex interconnect, or the VCSEL/detector array can also be covalently bonded to the IC or SERDES to maximize data bandwidth. The SERDES and VCSEL/detector array can also be produced in a single die using a process technology appropriate for both to maximize manufacturing efficiency.

Abstract: The invention includes both devices and methods of production. A device in accordance with the invention includes a top surface and a bottom surface, a through wafer via extending from the top surface to the bottom surface, an optoelectronic structure and an ion implanted isolation moat, wherein the optoelectronic structure and the through wafer via are enclosed within the isolation moat. A method in accordance with the invention is a method of producing a device that includes the steps of forming an optoelectronic structure, forming a through wafer via, extending from a top surface to a bottom surface of the device and forming an ion implanted isolation moat, wherein the through wafer via and the optoelectronic structure are enclosed by the isolation moat.

Abstract: The invention includes both devices and methods of production. A device in accordance with the invention includes a top surface and a bottom surface, a through wafer via extending from the top surface to the bottom surface, an optoelectronic structure and an ion implanted isolation moat, wherein the optoelectronic structure and the through wafer via are enclosed within the isolation moat. A method in accordance with the invention is a method of producing a device that includes the steps of forming an optoelectronic structure, forming a through wafer via, extending from a top surface to a bottom surface of the device and forming an ion implanted isolation moat, wherein the through wafer via and the optoelectronic structure are enclosed by the isolation moat.

Abstract: The invention includes both devices and methods of production. A device in accordance with the invention includes a top surface and a bottom surface, a through wafer via extending from the top surface to the bottom surface, an optoelectronic structure and an ion implanted isolation moat, wherein the optoelectronic structure and the through wafer via are enclosed within the isolation moat. A method in accordance with the invention is a method of producing a device that includes the steps of forming an optoelectronic structure, forming a through wafer via, extending from a top surface to a bottom surface of the device and forming an ion implanted isolation moat, wherein the through wafer via and the optoelectronic structure are enclosed by the isolation moat.

Abstract: The gated Transmission Line Model (GTLM) structure is a novel characterization device and measurement tool for integrated circuit process monitoring. This test structure has Schottky gates between the ohmic contacts of a TLM pattern. The gate lengths are varied and the gate-to- ohmic separations are kept constant to provide an accurate determination of several important FET channel parameters. It offers a precise method for measuring the FET source resistance which requires no parameter fitting and which works equally well on planar, self-aligned gate, and recessed gate FET's. In addition, the GTLM structure offers the only available means to measure sheet resistance of enhancement-mode FET channels. The gated-TLM structure can also be used to find the effective free surface potential. The structure may be combined with capacitance-voltage analysis or geometric magnetoresistance analysis to create mobility and doping profile of actual FET channels.