Patents by Inventor Steven M. Bidermann

Steven M. Bidermann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Diagnostic systems and methods of finite state machines
    Patent number: 9524007
    Abstract: In one embodiment, a power management integrated circuit comprises a finite state machine having a first terminal to receive a digital command signal, a second terminal to receive a clock signal, and a third terminal to receive a first reset signal to reset the finite state machine into a predetermined operational state. A plurality of diagnostic registers is configured to store a signal state of the digital command signal or a clock state of the clock signal, or both in response to the first reset signal. The diagnostic registers are configured to maintain the signal state or the clock state, or both after powering down of the power management integrated circuit in response to the first reset signal. The diagnostic registers are configured to allow retrieval of the stored signal state or the stored clock state, or both upon power on of the power management integrated circuit.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: December 20, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Raymond Keith Rosik, Steven M. Bidermann
  • DIAGNOSTIC SYSTEMS AND METHODS OF FINITE STATE MACHINES
    Publication number: 20150220123
    Abstract: In one embodiment, a power management integrated circuit comprises a finite state machine having a first terminal to receive a digital command signal, a second terminal to receive a clock signal, and a third terminal to receive a first reset signal to reset the finite state machine into a predetermined operational state. A plurality of diagnostic registers is configured to store a signal state of the digital command signal or a clock state of the clock signal, or both in response to the first reset signal. The diagnostic registers are configured to maintain the signal state or the clock state, or both after powering down of the power management integrated circuit in response to the first reset signal. The diagnostic registers are configured to allow retrieval of the stored signal state or the stored clock state, or both upon power on of the power management integrated circuit.
    Type: Application
    Filed: February 4, 2014
    Publication date: August 6, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Raymond Keith Rosik, Steven M. Bidermann