Patents by Inventor Steven M. Cea

Steven M. Cea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7851291
    Abstract: A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: December 14, 2010
    Assignee: Intel Corporation
    Inventors: Lucian Shifren, Jack T. Kavalieros, Steven M. Cea, Cory E. Weber, Justin K. Brask
  • Publication number: 20090230480
    Abstract: A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed.
    Type: Application
    Filed: May 26, 2009
    Publication date: September 17, 2009
    Inventors: Lucian Shifren, Jack T. Kavalieros, Steven M. Cea, Cory E. Weber, Justin K. Brask
  • Patent number: 7566605
    Abstract: A method for selectively relieving channel stress for n-channel transistors with recessed, epitaxial SiGe source and drain regions is described. This increases the electron mobility for the n-channel transistors without affecting the strain in p-channel transistors. The SiGe provides lower resistance when a silicide is formed.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: July 28, 2009
    Assignee: Intel Corporation
    Inventors: Lucian Shifren, Jack T. Kavalieros, Steven M. Cea, Cory E. Weber, Justin K. Brask